隨著半導體產業的發展，元件的微縮的過程中遭遇了物理上的挑戰，特別是在抑制短通道效應方面，因此在22奈米技術節點以後多閘極電晶體成為了首要的選擇。論文中我們將包覆式閘極電晶體與鰭式電晶體設計成擁有相似的閘極控制能力並加以比較，我們發現包覆式閘極電晶體雖然有較高的驅動電流，但在元件延遲(intrinsic delay)上鰭式電晶體卻擁有較好的表現。
在晶片設計上，靜態隨機存取記憶體佔有較大的體積以及產生較多的漏電，因此其被設計成high density (HD)、low voltage (LV)、high performance (HP)等組態，在此論文中我們模擬了不同元件所組成的不同組態的靜態隨機存取記憶體的寫入與讀取特性並分析其中的差異。
此外我們也模擬了各種靜態隨機存取記憶體可容忍的誤差並推估出其最小操作電壓值，並以由全包覆式閘極電晶體所組成的靜態隨機存取記憶體為例子將其做最佳化設計，成功的藉由擴大傳輸閘部分的電晶體來增加寫入能力以降低最小操作電壓值，然而此最佳化方法卻不適用於鰭式電晶體，雖然在靜態隨機存取記憶體的面積上有所犧牲，但相較於鰭式電晶體，全包覆式閘極電晶體在靜態隨機存取記憶體的設計上有更大的潛力與彈性。

As the semiconductor industry continues to advance, it has encountered many physical limitations, mostly related to short-channel effects (SCEs). Below node 22, the multi-gate structure has become the solution to improve the gate controllability. In this thesis, we benchmark 6T-SRAM of GAA MOSFETs and FinFETs and present the performance of both devices. We find that GAA MOSFETs with stacking technique provide higher drive current (per pitch) than FinFETs do. However the intrinsic delay (CV/ID) property is contrary. Static random access memory (SRAM) occupies a large portion of die size and consumes most of the standby leakages. 6T-SRAM has been designed as different configurations for high density (HD), low voltage (LV) and high performance (HP). Using a calibrated compact model, we can project the SNM and writeability of the 6T-SRAM for both devices in different configurations. And the characteristics of 6T-SRAM for all combination are demonstrated.
The yield estimation is also done by the calibrated macro-model. The yield estimation and the minimum cell operation voltage (Vmin) for all design combinations of SRAM are presented in this work. By adjusting the channel width of the pass-gate devices, we optimize the GAA MOSFET SRAM in LV configuration to improve Vmin. However, this method can not be used for FinFETs. Although it suffers from the area penalty, the GAA MOSFETs show the potential for SRAM design.

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