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研究生： 王南元
Wang, Nan-Yuan
論文名稱： 一個使用2.5-bit預測電容切換機制的十位元一億一千萬取樣頻率逐漸趨近式類比至數位轉換器
A 10-bit 110-MS/s SAR ADC with 2.5-bit Predictive Capacitor Switching Procedure
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 英文
論文頁數： 92
中文關鍵詞： 類比至數位轉換器 、逐漸趨近式 、逐漸趨近式類比至數位轉換器
外文關鍵詞： ADC, SAR ADC, SAR, analog-to-digital converter, successive approximation, high-speed, low-power
相關次數： 點閱：96  下載：12 
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    • 本論文提出的一個使用2.5-bit預測電容切換機制的十位元一億一千萬取樣頻率逐漸趨近式類比至數位轉換器。此新的電容切換機制加快了類比至數位轉換器的操作速度，並且有效地減少電容陣列所消耗的切換能量。除此之外，為了更進一步增進取樣頻率與降低能量消耗，此逐漸趨近式類比至數位轉換器也採用了非同步控制與單調式電容切換的技巧。
    本設計使用台積電90-nm 1P9M CMOS製程來實作晶片，其核心電路的面積為277 μm x 275 μm。根據佈局後模擬的結果，此晶片在每秒一億一千萬次取樣的操作速度下，總消耗功率為1.886 mW、有效位元數為9.81 bit。量測結果顯示此晶片在每秒八千萬次取樣的操作速度下，總消耗功率為1.343 mW、有效位元數為7.92 bit。每次資料轉換所消耗的能量分別只有19.13 fJ 以及69.3 fJ。

    This thesis presents a 10-bit 110-MS/s SAR ADC with a proposed 2.5-bit predictive capacitor switching scheme. This new switching scheme enhances the operating speed and significantly reduces the power consumption in the capacitor array for a SAR ADC. In addition, the proposed ADC adopts the asynchronous processing technique and monotonic capacitor switching procedure to further improve both speed and power consumption. This work is fabricated in TSMC 90-nm 1P9M CMOS process, and occupies 277 μm x 275 μm active area. The post-layout simulation results show that the total power consumption is only 1.886 mW, and the effective number of bits (ENOB) is 9.81 bit at 100-MS/s. The measurement results show that the total power consumption is 1.343 mW, and ENOB is 7.92 bit at 80-MS/s. The figure-of-merit (FoM) achieves as low as 19.13 fJ/conv.-step and 69.3 fJ/conv.-step, respectively.

    Abstract (in Chinese) I Abstract (in English) II Acknowledgement III Contents V List of Figures VII List of Tables X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Fundamentals of Analog-to-Digital Converter (ADC) 5 2.1 Introduction 5 2.2 Analog-to-Digital Converter (ADC) 6 2.3 ADC Performance Metrics 7 2.3.1 Resolution and Accuracy 8 2.3.2 Static Specifications 9 2.3.3 Dynamic Specifications 13 2.4 High-Speed ADC Topologies 17 2.4.1 Flash ADC 18 2.4.2 Two-Step ADC 20 2.4.3 Pipelined ADC 22 2.4.4 Time-Interleaved ADC 24 Chapter 3 Successive Approximation (SAR) ADC 26 3.1 Introduction 26 3.2 The Architecture of SAR ADC 27 3.2.1 DAC-Based SAR ADC 27 3.2.2 Charge-Redistribution SAR ADC 29 3.3 Asynchronous Processing Technique 33 3.4 Energy-Efficient Capacitor Switching Procedure 36 3.4.1 Conventional Capacitor Switching Procedure 36 3.4.2 Split Capacitor Switching Procedure 37 3.4.3 Monotonic Capacitor Switching Procedure 39 3.4.4 Analysis of Switching Energy 41 3.4.5 Summary of Capacitor Switching Procedures 45 3.5 Predictive Capacitor Switching Procedure 46 3.5.1 Splitting Monotonic Capacitor Switching Procedure 46 3.5.2 Predictive Capacitor Switching Procedure 48 Chapter 4 A 10-bit 110-MS/s Asynchronous SAR ADC 51 4.1 Motivation 51 4.2 Proposed 2.5-bit Predictive Capacitor Switching Procedure for SAR ADC 52 4.3 Architecture and Operation 55 4.3.1 Architecture of Proposed SAR ADC 55 4.3.2 Operation of Proposed SAR ADC 57 4.3.3 DAC Incomplete Settling Tolerance 60 4.4 Circuit Implementation 61 4.4.1 S/H Circuit 61 4.4.2 Timing Controller 63 4.4.3 Dynamic Comparator 65 4.4.3 Capacitor Array 67 4.4.4 Sub-DAC 69 4.5 Layout and Floor Plan 70 4.6 Simulation Results 71 4.7 Measurement 76 4.7.1 Chip Micrograph and Measurement Setup 76 4.7.2 Measurement Results 78 4.8 Comparison and Discussion 82 Chapter 5 Conclusion and Future Work 84 Bibliography 87

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