本論文提出一個新的發射機架構，在電路上減少了傳統發射機電路中鎖相迴路與混頻器的使用，並且在輸出級使用了非線性的功率放大器，也因此整體電路能達到低功率消耗的目標，此外本發射機使用三角積分調變器來達成高解析度的多通道通訊，並且提出一個新的機制去消除三角積分調變器所產生的高頻雜訊，利用分數型注入鎖定來取代傳統迴路濾波器的使用；在調變方面則使用二進位頻率鍵移調變，而整體的發射機輸出頻帶則操作在工業科學及醫學頻段中規定的四百三十三百萬赫茲。
本論文的在前半段章節介紹電路上的觀念，例如:三角績分調變器、注入鎖定，及子電路的架構與實現，章節四則為量測考量的介紹及結果，總共有兩顆晶片在本論文中介紹，分別為:注入鎖定式分數型頻率合成器及利用注入鎖定實現多通道頻率鍵移通訊的低功耗發射機，兩顆晶片皆為TSMC18RF製程，第一顆晶片利用現場可編輯邏輯閘陣列(FPGA)來驗證分數型注入鎖定晶片，晶片面積為 1.158 x 1.158 mm2 ；第二顆晶片的部分則為發射機功能的驗證及量測考量介紹，在模擬的環境下，整體電路的功耗為727µ watt，而輸出的功率為-21.3dBm，資料速率為100kbps，晶片的面積為1.447 x 1.447 mm2。

This thesis proposes a new architecture of transmitter which eliminates the sub-block utilization in traditional transmitter such as PLL and mixer. Besides, with the application of nonlinear power amplifier, the low power design can be achieved. This transmitter also has the characteristic of multi-channel communication in fine resolution which is fulfilled with Delta-Sigma Modulator (DSM) and proposes a novel technique fractional injection locking to filter out the quantization frequencies resulting from DSM without the utilization of loop filter. With respect to modulation, this transmitter is based on Binary frequency shift keying (BFSK) modulation in ISM band (433 Mega Hz).
The preceding chapters introduce the concepts such as Delta-Sigma Modulator Injection Locking、and corresponding circuit implementation in proposed transmitter. The measurement results are given in chapter four. There are two chips in this thesis and they are fractional-N injection locking frequency synthesizer and low power multi-channel FSK transmitter with injection locking technique. All the chips are based on TSMC18RF process. The preceding one is to validate the proposed technique of quantization frequencies filtering with the aid of FPGA. This chip area is 1.158 x 1.158 mm2. The second chip is to validate the proposed transmitter. The power consumption of transmitter in simulation is 727µ watt with -21.3dBm output power and data rate is 100kbps. The chip area is 1.447 x 1.447 mm2.

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