電流驅動式數位類比轉換器擁有高速的特性，而且現在也廣泛應用在寬頻的通訊系統。但是電流驅動式數位類比轉換器因有元件不匹配特性限制它的解析度。元件不匹配會在頻譜上造成非線性諧波而降低拒斥動態範圍值(SFDR)。這篇輪文提出一個新的演算法稱為隨機多重資料權重平均演算法可以有效克服諧波失真。隨機多重資料權重平均演算法打散諧波，將能量平均分配到noise floor而增加SFDR。我們也在這篇論文中用低複雜數位電路來實現隨機多重資料權重平均演算法。另外論文也推導出相關的數學式子和定量分析。
　　我們也在這篇論文中製作一個十六位元高速數位類比轉換器。這個數位類比轉換器分成三個部分：六個最大位元(MSB)轉換成熱碼，而且這部分也使用隨機多重資料權重平均演算法；接下來五個位元(ULSB)也是轉換成熱碼，五個最小位元(LLSB)則維持使用二元碼。另外在類比部分也提出一個新的開關配置順序稱為Q的N次方旋轉式開關順序來補償元件不匹配特性。Q的N次方旋轉式開關順序能補償一階和二階的元件不匹配分布。另外也設計一個新的高速鎖栓器來增加數位類比轉換器的速度。
　　這個數位類比轉換器採用台積電1P5M,0.25um製程來實現，整個晶片面積是1.9x0.9mm2。佈局後的模擬結果證實此數位類比轉換器可以操作在40MHz轉換頻率，類比電壓2.7伏特，數位電壓2.2伏特。當訊號頻率是780KHz時，SFDR可以達到102dBc。訊號頻率升到8MHz和18MHz時,SFDR分別是92dBc和84dBc。

　　Current-steering DACs have intrinsic high-speed characteristics and are commonly used in wide-band communication systems today. However, element mismatch will cause harmonic distortion and thus limits their performance. This thesis proposes a new algorithm called Random Multiple Data Weighted Averaging (RMDWA) to reduce harmonic distortions due to element mismatch. RMDWA can be used to randomize tones such that spurious-free dynamic range (SFDR) and multi-tone power tone (MPTR) are increased. In addition, low-complexity digital circuit used to implement RMDWA algorithm is presented in this thesis. Performance equations and quantitative performance analyses of RMDWA are also derived.
　　A 16-bit high-speed current-steering DAC is implemented in this thesis. The DAC includes a 6-bit thermometer-decoded MSB with RMDWA algorithm, a 5-bit thermometer-decoded upper LSB (ULSB) and a 5-bit binary-decoded lower LSB (LLSB). The new QN rotated-walk switching scheme is also proposed to obtain high accuracy without trimming or tuning. QN rotated-walk switching scheme can effectively compensate 1st–order and 2nd–order errors caused by current sources mismatch. In addition, a new latch is designed to increase conversion speed and reduce noise. The post-layout simulation shows that it can achieve 102/94/84dBc SFDRs under a 40-MHz clock rate with 780KHz/5MHz/18MHz signal frequencies, respectively. With 2.7V analog and 2.2V digital supplies, it has power consumption of 112mW for a clock rate of 40 MHz. The DAC is fabricated with TSMC 0.25um single-poly, five-metal process. The active die area is 1.9mm x 0.9mm.

1.J.Sevenhans and Z.Chang, “A/D and D/A conversion for telecommunication,” IEEE Circuits and Dev. Mag., vol. 14, pp. 32-42, Jan. 1998

2.P. Hendriks, “Specifying communications DACs,” IEEE spectrum, vol. 34, pp. 58-69, July 1997.

3.D. Mercer, “A 16bit D/A converter with increased spurious-free dynamic range,” IEEE, J. Solid-State Circuits, vol. 29, pp. 1180-1185, Oct. 1994.

4.B. Tesch and J. Garcia, “A low-glitch 14-bit 100MHz D/A converter,” IEEE, J. Solid-State Circuits, vol. 32, pp. 1465-1469, Sept. 1997.

5.Alex R. Bugeja, Bang-sup Song, “ A self-trimming 14-b 100MS/s CMOS DAC,” IEEE, J. Solid-State Circuits, vol. 35, pp. 1841-1852, Dec. 2000.

6.R. Hester et al., “CODEC for echo-canceling full-rate ADSL modems,” in ISSCC Dig. Tech. Papers, 1999, pp. 242-243.

7.D. Groeneveld et al., “A self-calibration technique for monolithic high-resolution D/A converters,” IEEE, J. Solid-State Circuits, vol. 24, pp. 1517-1522, Dec. 1989.

8.J. Bastos et. al., “A 12 bit intrinsic accuracy high-speed CMOS DAC,” IEEE, J. Solid-State Circuits, vol. 33, pp. 1959-1969, Dec. 1998.

9.G. Van der Plas et. al., “A 14-bit intrinsic accuracy Q2 random-walk CMOS DAC,” IEEE, J. Solid-State Circuits, vol. 34, pp. 1708-1718, Dec. 1999.

10.Y. Nakamura, T. Miki et. al., “An 80-MHz 8-bit CMOS D/A Converter,” IEEE, J. Solid-State Circuits, vol. 21, pp. 983-988, Dec. 1986.

11.R. T. Baird, T. S. Fiez, “Linearity enhancement of multibit A/D and D/A converters using data weighted averaging,” IEEE Trans. Circuits Syst. , vol. 42, pp. 753-762, Dec. 1995.

12.R. E. Radke, A. Eshraghi, and T. S. Fiez, “A 14-bit current-mode DAC based upon rotated data weighted averaging,” IEEE, J. Solid-State Circuits, vol. 35, pp. 1074-1084, Dec. 2000.

13.S. Chan, J. Cao er. al., “A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multinit delta-sigma modulation at 8 oversampling ratio,” IEEE, J. Solid-State Circuits, vol. 35, pp. 1820-1828, Dec. 2000.

14.K. D. Chen, H. R. Yeng, T. H. Kuo,” A wideband CMOS sigma-delta modulator with incremental data weighted averaging,” IEEE, J. Solid-State Circuits, vol. 37, pp. 11-17, Jan. 2002.

15.R. M. Gray and T. G. Stockham, Jr., “Dithered quantizers,” IEEE Inform. Theory, vol. 39, pp. 805-812, May 1993.

16.Chi-huang and Klaas Bult, “A 10-b, 500-Msamples CMOS DAC in 0.6mm2”, IEEE, J. Solid-State Circuits, vol. 33, pp. 1948-1958, Dec. 1998.

17.M. Copeland et. al., “Characterization and modeling of mismatch in MOS transistors for precision analog design”, IEEE, J. Solid-State Circuits, vol. SC-21, pp. 1057-1066, Dec. 1986.

18.M. J. M. Pelgrom et. al. ”Matching properties of MOS transistors”, IEEE, J. Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.

19.Design Documents for TSMC 0.25um 1P5M Mixed Signal Process.

20.B. Razavi, “principles of Data Conversion system Design. Piscataway,” NJ: IEEE Press, 1995, pp. 62-63

21.O.Nys and R. Henderson, “An analysis of dynamic element matching techniques in sigma-delta modulation,” in Proc. ISCAS’96, Atlanta, GA, May 12-15, 1996, pp. 231-234