本論文為設計應用於 2.4/24 GHz 雙頻接收機前端電路之子電路設計，其中分為兩部分：第一部分為 2.4 GHz 接收機前端電路；第二部分為 24 GHz 接收機前端電路。皆使用 TSMC 0.18μm CMOS 1P6M 製程實現設計。
2.4 GHz 接收機前端電路由低雜訊放大器與混頻器組成，低雜訊放大器部分採用電容交叉耦合對來達到 gm-boosting 的效果，在達到輸入匹配的同時相較於共閘極架構減少一半的功耗，且也能改善共閘極架構雜訊指數過高的問題；混頻器採用被動式混頻器的架構，有較佳的線性度且沒有直流消耗；基頻放大器使用共閘極放大器並在輸出端使用一低通濾波器，將混頻後之諧波項給濾除，只留下所需基頻訊號。2.4 GHz接收機前端電路採用供應電壓 1.2V，量測結果顯示轉換增益為 20 dB；雜訊指數為 9.1dB；P1dB 為-22 dB；IIP3 為-13 dB；功率消耗為 3.78 mW。
24 GHz 接收機前端電路主要架構由三級串接低雜訊放大器與主動式混頻器組成，透過三級串接放大器能在達到高增益與低雜訊指數的同時兼顧到線性度，將提高接收機的靈敏度；混頻器採用主動式架構，並加上級間電感提升電路整體的增益與線性度；輸出端緩衝放大器使用共汲級架構。24 GHz 接收機前端電路採用供應電壓 1.8V，量測結果顯示轉換增益為 14 dB；雜訊指數為 7 dB；P1dB 為-26 dB；IIP3 為-21.5 dB；功率消耗為 31.14 mW。

This thesis presents the subcircuit designs of 2.4/24 GHz radio frequency receiver front end circuit, which can be divided into two parts by the operating frequency. The first part is a design of 2.4 GHz receiver front end circuit, the second part is a design of 24 GHz receiver front end circuit. All the circuits are fabricated by the TSMC 0.18μm CMOS process.
2.4 GHz receiver front end circuit is composed of low noise amplifier and mixer. Low noise amplifier adopts the gm-boosting technique is implemented by a capacitor cross-coupled pair. Not only match the input impedance but reduce half of the power consumption and have lower noise contribution compared to common gate structure at that same time. The Mixer utilizes a passive mixer, the best advantage of which is it has no DC consumption and better linearity than the active mixer. A common gate amplifier is used to be a baseband amplifier, and there is a low pass filter in its output node to filter out the unwanted harmonics which generates by mixing. The proposed 2.4GHz receiver front end circuit achieves the conversion gain of 20 dB with the noise figure of 9.1 dB, provides the P1dB and IIP3 of -22 dB and -13 dB, while taking the 3.78 mW from a 1.2 V supply voltage.
24 GHz receiver front end circuit is composed of three stages low noise amplifier and active mixer. The three stages low noise amplifier can simultaneously achieve high gain, low noise, and good linearity by proper design, and it will increase the sensitivity of the receiver system. The mixer in this system is an active mixer, which can raise the conversion gain and linearity by the interstage inductor. In the end, the output buffer adopts the common drain structure. 24GHz receiver front end circuit achieves the conversion gain of 14 dB with the noise figure of 7 dB, provides the P1dB and IIP3 of -26 dB and -21.5 dB, while taking the 31.14 mW from a 1.8 V supply voltage.

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