目前在硬體設計的範疇中，整個設計的流程由於產品更新速度的大幅增加，設計及驗證的時間越來越具急迫性。因此，近年來軟硬體協同設計的概念越來越被重視，並且也可由這個方式達到軟硬體同時進行設計及驗證的功能。
本篇論文基於在一個包含QEMU及CoWare的協同設計平台上[16]，對於整體模擬的架構做分析及效能的改善。這個架構是由QEMU端模擬ARM處理器，並以Socket介面連接至模擬硬體的CoWare端以達成軟硬體協同設計模擬。
經由分析後發現由於模擬的架構會大量使用到Socket間的溝通，造成在Socket介面部分由於傳輸時間過長而增加模擬時的負擔，因此本論文提出了以Shared Memory 介面取代 Socket介面做為軟硬體模擬間的溝通方式，增加整體模擬的效率平均可達到1.46倍，其中對於資料量最大的Benchmark “Bunny”速度可加快到1.6倍。
而對於CoWare端的ESL層級模擬，由於SystemC只支援single process的執行，因此本論文也提出一個約會程序平行模擬(Rendezvous Parallel Simulation)的概念，將硬體端負載較重的部分抽離出原本單一程序模擬的環境，並以外部Process的方式附加到原本的模擬平台上，再利用Shared Memory做為中介層，讓各個模擬程序的資料可以互相流通，使硬體模擬部份可以在原本應用CoWare及SystemC的架構中提升整個硬體模擬平台的模擬速度。對於產生一張3D圖像來說，這個方法可以改善模擬速度平均達到約3.6倍的速度。

Hardware-software co-designs are getting more and more important for complex SoC development. This thesis anylyzes a hybrid simulation system and improves the efficiency of the simulation based on a platform using QEMU and CoWare tool[16]. The co-simulation system includes QEMU simulating the ARM processor, and the CoWare tool simulating hardware with socket connecting both sides.
After analyzing the simulation structure, we find that the current simulation systrem has massive socket communications, and this significantly increases simulation overhead due to the long communication time of sockets. Therefore, this thesis presents a communication method to replace socket with shared memory to improve the simulation efficiency up to 1.46 times. For benchmark Bunny, the improvement is up to 1.6 times.
For ESL level simulation with CoWare, because SystemC library only supports single thread execution, this thesis also introduces a concept that extracts part of the heavy workload in hardware simulation and moves this part of simulation to a process outside of the CoWare platform. Shared memory is used to be the interface that exchanges the data for the two simulation processes. The hardware simulation with CoWare can then have better simulation efficiency, and the hardware simulation platform can speed up to about 3.6 times in average.

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