本論文利用互補式金氧半場效電晶體研究應用於全球定位系統接收機前端之射頻積體電路。一般而言，接收機大致上包含有放大器、混波器、震盪器及數位/類比轉換器等部分，而本論文主要著重在設計前端，即低雜訊放大器和混波器，而設計的晶片特色為可同時接收全球衛星定位系統之雙頻(L1、L5)訊號，本論文所研製的晶片均使用國家系統晶片中心提供之標準TSMC 0.18 製程，所有的晶片皆打鎊線至印刷電路板上進行量測。

在第一顆晶片中，設計包含有一雙頻低雜訊放大器及兩個雙頻混波器，低雜訊放大器採用兩級串接架構將訊號放大，而兩個雙頻混波器則採用雙端平衡式的架構，另外並做晶片的輸入與輸出匹配網路設計。

在第二顆晶片中，設計了一雙頻低雜訊放大器及一組同相/正交雙頻混波器，低雜訊放大器設計上採用疊接架構將訊號放大，之後則輸出至同相/正交雙頻混波器降頻，混波器主要採用單端平衡式的架構，本晶片另外還設計了一相移器，用以產生四相位的本地震盪頻率以提供同相/正交雙頻混波器使用。

This thesis presents the design and implementation of RFICs for receiver front end for GPS application. A GPS receiver relies on the case of amplifier, mixer, oscillators, A/D converter to provide digital IF data for signal acquisition, tracking, and navigation. This thesis focus on the design of the front end including the LNA (Low Noise Amplifier) and mixer. A distinctive of these chips is the circuits are designed dual frequency (L1, L5) GPS signals simultaneously. All of these chips to process are fabricated in TSMC standard 0.18 process. The measurements are performed on FR-4 test PCB with RFICs bounded.

The first chip includes one dual band LNA and two dual band mixers. The LNA uses cascade topology to amplify the signal and two mixers use double balanced topology. It also contains input/output matching networks. In contrast, the second chip includes one dual band LNA and one dual band I/Q mixer. The LNA uses cascade topology to amplify signal and I/Q mixers are use single balanced topology to downconvert signal. This chip also contains a phase shifter to generate four different phases’ LO signal to provide the I/Q mixers’ LO port.

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