隨著消費性電子產品市場的前進，越來越多不同的無線通訊系統標準與規範被制定。為了滿足這些系統需求，滿足特殊需求的單一RF子電路成為本論文的設計目標。在此次的作品中，選擇互補式金氧半(CMOS)製程來實現我們的電路是由於其具有高度整合性與低成本的特質。
在本論文中，設計並分析了兩個操作在K-band的除三注入鎖定除頻器與22-29-GHz 使用三倍頻電路的壓控振盪器。第一個實作是使用電流源注入(current-bleeding)與並聯共振(shunt-peaking)的兩個技巧而提高注入鎖定範圍(locking range)的除三注入鎖定除頻電路。此一電路是製作於 0.18-μm CMOS 1P6M製程並且操作在K-band。從量測的結果得知，此次設計的電路在輸入訊號0 dBm時的整體注入鎖定範圍為3.86 GHz。在提供電壓為1.2 V時的消耗功率為4.28 mW。量測結果顯示輸出二次與三次諧波對操作在8.4-GHz的輸出之抑制分別為38.05 dBc和37.89 dBc。在鎖定狀況下的量測結果顯示當頻率位移為1 MHz和輸入訊號是+4 dBm之下相位雜訊為-139 dBc/Hz。
第二個實作是使用互補式金氧半電晶體串聯耦合(CMOS series-coupled)的架構下輸出四相位的除三注入鎖定除頻電路。此次設計為利用修改過的傳統互補式金氧半電晶體串聯耦合電路結合除三注入鎖定除頻電路來四相位的輸出。此一電路也是製作於0.18-μm CMOS 1P6M製程。從量測的結果得知，此次設計的電路在輸入訊號0 dBm時的整體注入鎖定範圍為760 MHz。量測結果顯示輸出二次與三次諧波對操作在7.72-GHz的輸出之抑制分別為35.78 dBc和39.37 dBc。在輸入訊號是0 dBm的鎖定狀況下，量測結果顯示當頻率位移為100 KHz和1 MHz之下相位雜訊分別為-119 dBc/Hz和-143.6 dBc/Hz。
最後一個實作為操作頻率在22-29 GHz利用三倍頻電路的寬頻壓控振盪器設計。此電路為低頻產生電路和三倍頻電路所組成而藉此可得到很好的頻率調動能力。此電路也是實現於0.18-μm CMOS 1P6M製程(現正在晶片製作中)。從模擬的結果顯示，輸出的頻率範圍是6.67-GHz並且功率消耗為9.4 mW。模擬的相位雜訊在輸入訊號是0 dBm時是-104.2 dBc/Hz並且FOMT是-191.4 dBc/Hz。跟之前發表的文獻結果比較，此電路具有最寬的頻率可調範圍。

Due to the advances of market in consumer electronic products, many different standards and regulations of wireless communication system have been established. To fulfill the system requirements, the development of each individual RF circuit blocks for a special purpose is our design target in this thesis. In this work, we choose CMOS technology to implement the RF blocks such as frequency divider and oscillator due to its high integration capability and low cost.
In this thesis, two divide-by-three injection-locked frequency dividers (ILFDs) within the frequency range of K-Band and a 22-29-GHz voltage-controlled oscillator (VCO) by using frequency tripling scheme have been proposed and characterized. The first work is an enhanced locking range divide-by-three ILFD with shunt-peaking and current-bleeding techniques. This work was fabricated in 0.18-μm CMOS 1P6M technology and it is operated in K-band. From the measurement results, the proposed circuit the total locking range is 3.86 GHz for an input injection power of 0 dBm. The power consumption is 4.28 mW at a supply voltage of 1.2V. The second- and third-order harmonic suppressions are 38.05 dBc and 37.89 dBc, respectively, for a divided output frequency of 8.4 GHz. The output phase noise under lock is -139 dBc/Hz at an offset of 1 MHz from the oscillation frequency as the input injection power is of +4 dBm.
The second work is a 24-GHz quadrature divide-by-three injection-locked frequency divider with CMOS series-coupled topology. The quadrature outputs are generated by employing a modified topology which comes from a conventional CMOS series-coupled quadrature LC-oscillator with divide-by-three ILFD. This work was fabricated in 0.18-μm CMOS 1P6M technology, too. The measured locking range is 760 MHz for an injection power of 0 dBm. The second- and third-order harmonic suppressions are about 35.78 dBc and 39.37 dBc, respectively, for a divided output frequency of 7.72 GHz. The measured phase noises under lock are -119 dBc/Hz and -143.6 dBc/Hz at 100-KHz and 1-MHz offsets, respectively, with an injection power of +0 dBm.
The last work is a 22-29-GHz wide tuning range oscillator by using the frequency tripling scheme from a VCO of 7~9 GHz. The proposed work has two stages which are composed of a low frequency generator and frequency tripler to attain the excellently wide frequency tuning capability. This work was also implemented by 0.18-μm CMOS 1P6M technology (now in chip fabrication). From the simulation results, tuning rage is 6.76 GHz and core dissipation power is 9.4 mW. The simulated phase noise is -104.2 dBc / Hz at 1 MHz offset frequency and figure-of-merit with tuning range (FOMT) is -191.4 dBc / Hz. The proposed work has achieved highest tuning range than previous published results.

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