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研究生： 陳泱寯
Chen, Yang-Jun
論文名稱： 一個七位元每秒取樣五百六十億次時間交錯式時域類比數位轉換器
A 7-bit 56GS/s Time-interleaved Time Domain ADC
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2026
畢業學年度： 114
語文別： 英文
論文頁數： 76
中文關鍵詞： 時域類比數位轉換器 、時間交錯式 、電壓時間轉換器 、時間數位轉換器 、多相時脈產生器 、輸入緩衝器
外文關鍵詞： Time-Domain Analog-to-Digital Converter (TD-ADC), Time-Interleaved (TI), Voltage-to-Time Converter (VTC), Time-to-Digital Converter (TDC), Multi-phase Clock Generator, Input Buffer
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    • 本論文提出一款每秒取樣五百六十億次時間交錯式時域類比數位轉換器，該電路整合了輸入緩衝器與八相時脈產生器。為了極小化取樣時脈抖動，本設計採用了注入技術。每個子通道皆採用時域類比數位轉換器架構，由電壓時間轉換器與時間數位轉換器組成，單一通道取樣率可達每秒七十億次。因此，僅需八個子通道即可達成總計 56 GS/s 的取樣速率。得益於較低的交錯因子，以及時域類比數位轉換器中基於主動元件量化技術的面積優勢，本設計在展現極具競爭力的晶片面積之餘，仍保有與逐漸趨近式架構相當的功耗效率。
    本晶片採用 TSMC N16 FFC+ 製程設計，核心面積僅為0.06 mm²。在 0.8 V 供應電壓與每秒取樣五百六十億次取樣率下，功耗為126毫瓦。實驗結果顯示，在低輸入頻率下之信號雜訊失真比為26.36 dB；當輸入頻率達20 GHz時，受殘餘時間偏移影響，SNDR為11.24 dB。對應之能量效率優值為751 fJ/conv-step。

    This thesis presents a 56 GS/s time-interleaved (TI) time-domain ADC (TD-ADC), which integrates an input buffer and an eight-phase clock generator. To minimize sampling clock jitter, an injection-locking technique is employed. Each sub-channel utilizes a TD-ADC architecture consisting of a Voltage-to-Time Converter (VTC) and a Time-to-Digital Converter (TDC), capable of reaching a sampling rate of 7 GS/s. Consequently, the aggregate 56 GS/s rate is achieved with only eight sub-channels. Benefiting from the reduced interleaving factor and the area-efficient nature of active-component-based quantization in TD-ADCs, this design demonstrates a competitive area footprint while maintaining power efficiency comparable to SAR-based architectures. The proof-of-concept chip was fabricated in the TSMC 16nm (N16) FFC+ process, occupying a core area of only 0.06 mm2. Under a 0.8 V supply at 56 GS/s, the ADC consumes 125 mW. Experimental results show an SNDR of 26.36 dB at low input frequencies. At a 20 GHz input frequency, the SNDR is 11.24 dB due to residual timing skew. The corresponding Figure of Merit is 751 fJ/conv-step.

    摘要 I Abstract II Table of Content IV List of Tables VI List of Figures VI Chapter 1 Introduction 1 1.1 background 1 1.2 organization 2 Chapter 2 Time Domain ADC 4 2.1 abstract 4 2.2 introduction to time domain adc 4 2.3 key building blocks of time domain adc 5 2.3.1 Voltage-to-Time Converter (VTC) 5 2.3.2 Time-to-Digital Converter (TDC) 8 Chapter 3 Time-Interleaved ADC 13 3.1 introduction 13 3.1.1 Single-Channel Sampling 14 3.1.2 Time-Interleaved Sampling 17 3.2 mismatch of ti adc 22 3.2.1 Offset Mismatch 23 3.2.2 Gain Mismatch 25 3.2.3 Timing Skew Mismatch 28 Chapter 4 A 7-bit 56GS/s Time-interleaved Time Domain ADC 32 4.1 introduction 32 4.2 Architecture and Design Considerations 32 4.2.1 Overall Architecture 32 4.2.2 Necessity for Input Buffer in High Speed TI-ADC 33 4.2.3 High Speed ADC Clock Requirement 34 4.3 circuit building block 35 4.3.1 Input Buffer 35 4.3.2 Sub-Channel Sample and Hold 37 4.3.3 Sub-Channel VTC 38 4.3.4 Sub-Channel TDC 39 4.3.5 Multi-Phase Clock Generator 44 4.3.6 Down Sampling for Measurement 46 Chapter 5 Simulation and Measurement Results 48 5.1 layout and chip floor plan 48 5.2 simulation results 50 5.3 chip photo and measurement setup 52 5.4 measurement result 56 Chapter 6 Conclusion and Future Work 61 6.1 Conclusion 61 6.2 Future work 61 6.2.1 Sub-Channel ADC 61 6.2.2 Input Buffer 62 6.2.3 Multi-Phase Clock Generator 62 6.2.4 Down-Sampling Circuit 63 Reference 64

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