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研究生：	盧世權 Lu, Shih-Chuan
論文名稱：	基於對偶密碼器與合成場的AES設計之研究 On the Design of AES Based on Dual Cipher and Composite Field
指導教授：	賴溪松 Laih, Chi-Sung
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2003
畢業學年度：	91
語文別：	英文
論文頁數：	130
中文關鍵詞：	合成場、對偶密碼器
外文關鍵詞：	AES, ASIC, composite field, dual cipher, S-box, SubBytes
相關次數：	點閱：74 下載：2
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2001年，NIST正式訂定Rijndael演算法為新一代加密標準(AES，Advanced Encryption Standard)，以取代使用多年的DES (Data Encryption Standard)。AES是以簡單代數運算為架構的對稱式密碼系統，其主要是由SubBytes、ShiftRows、MixColumns與AddRoundKey四個轉換與金鑰產生器所組成。於2002年，Barkan與Biham對於以代數運算為架構的AES，提出下面的觀點：我們若替換AES密碼器SubBytes的仿射轉換(Affine Transformation)、MixColumns的擴散多項式，以及乘法運算所需的不可分解多項式(Irreducible polynomial)之後，我們可以得到等同於AES的對偶密碼器(Dual Cipher)。對偶密碼器的存在拓展開AES可討論的空間。其中一個可能的討論方向，就是應用對偶密碼器來取代AES密碼器進行加解密運算，以得到最佳化的速度。然而至今為止，仍未有人確實提出以對偶密碼器來實現AES的設計方法，甚至亦無法確認對偶密碼器的應用，是否能產生一個更快速的AES密碼器。
為了探討對偶密碼器應用的可行性，在本論文中，我們將深入研究對偶密碼器的理論。對於實現對偶密碼器的應用，我們將目標著眼於SubBytes (S-box)硬體設計中面積與速度的最佳化。在SubBytes的運算上，我們使用合成場來代替查表的動作，並且利用對偶密碼器改變運算所在的場，以得到面積與速度最佳化SubBytes的設計。相較於已發表之文獻，我們設計的SubBytes縮減了1/6的面積，並縮減了1/4的路徑延遲。

In 2001, NIST (National Institute of Standards and Technology) chose the Rijndael algorithm as the AES (Advanced Encryption Standard) for the sake of replacing the original encryption standard DES. AES is a block cipher system based on simple algebraic operations. Operating over the algebraic Galois field GF(2^8), AES has four primitive functions, SubBytes, ShiftRows, MixColumns, and AddRoundKey. In 2002, Barkan and Biham issued that if we replace all the constants in AES, including replacement of the irreducible polynomial, the coefficients of the MixColumns operation, the affine transformation in the SubBytes, etc, we can create new dual ciphers. The existence of dual ciphers brings the discussion of AES to a wide and interesting region. A possible application of dual ciphers “might be” an optimization of the speed of the cipher if operations execute in dual cipher instead of the AES. However, until now, there’s no implementation method proposed that indeed speed up the encryption using the dual cipher. Even more, we are not sure if the application of dual cipher can generate a faster cipher or not.
For investigating the feasibility of the dual cipher’s applications, in this thesis, we will discuss about the dual cipher in depth. To realize the application of dual AES, our aim is to divert to the optimization of the area and speed in the hardware design of SubBytes(S-box). The operations of SubBytes compute with using composite field arithmetic instead of simply using look-up table. To obtain the optimal efficiency, we change the field of executing by using the dual cipher. Comparing with the literature published, in our design of SubBytes, the cost of area is decreased by 1/6 and the cost of delay is decreased by 1/4.

Chapter 1   Introduction	1
	1.1   Research Motives	1
	1.2   Thesis Outline	2
	1.3   Our Contributions	3
Chapter 2   Preliminaries	5
	2.1   The AES Algorithm	5
	      2.1.1   Operations and Basic Operations	5
	      2.1.2   The Cipher	7
	      2.1.3   The Key Expansion	12
	      2.1.4   The Inverse Cipher	14
	2.2   The Dual Cipher	15
	2.3   An Example of SubBytes Implementation	18
	      2.3.1   The Composite Field	18
	      2.3.2   An Example of SubBytes Implementation	20
Chapter 3   The Optimal Design of SubBytes	25
	3.1   The Discussion of Dual AES	25
	      3.1.1   Generalized Representation Dual AES	26
	      3.1.2   How Does the Dual AES Work?	28
	      3.1.3   Mapping From AES into Dual AES	34
	3.2   SubBytes Implementation Based on Composite Field 	38
	      3.2.1   Efficient Inverse in GF(28)	39
	      3.2.2   The Architecture of SubBytes	40
	3.3   Optimizing the Design of SubBytes by Operating in Dual AES	44
	      3.3.1   Cost Analysis	46
	      3.3.2   Evaluation of the SubBytes	48
	3.4   A Design of SubBytes Based on Dual AES and Composite Field	52
	      3.4.1   Our Design 1 of SubBytes	53
	      3.4.2   Complexity of the Design 1	57
	3.5   Improved Architecture of SubBytes	58
	      3.5.1   Merging the Components	58
	      3.5.2   The Improved Architecture	61
	3.6   A Design of SubBytes Using the Improved Architecture	65
	      3.6.1   Our Design 2 of SubBytes	65
	      3.6.2   Complexity of the Design 2	69
	3.7   The Optimal Design of SubBytes Based on Dual AES and Composite Field	70
	      3.7.1   Our Design 3 of SubBytes	71
	      3.7.2   Complexity of the Design 3	74
	3.8   Implemented Result	76
Chapter 4   The Design of AES	77
	4.1   Optimizing the Design of AES Based on the Dual Cipher	77
	      4.1.1   Cost of Functions in Dual AES	78
	      4.1.2   Evaluation the Design of AES	79
	4.2   The Design of AES with Using the Optimal SubBytes	81
Chapter 5   Conclusion and Future Work	87
Bibliography	89
Appendix A	93
Appendix B	97
                                    

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校內：2006-07-11公開
校外：2008-07-11公開

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