在現今的一些類比電路佈局當中，如何保持電容的精確比例是一個很重要的議題。通常我們會將影響電容準確性的來源分成系統和隨機不匹配這兩種。最近已經存在一些研究討論如何克服這兩種不匹配的電容陣列擺置，但是尚未有研究討論到電容陣列中繞線的問題。在此篇研究中，我們探討了電容陣列當中電容的擺置結果如何直接影響到繞線通道所需要的寬度，並且間接決定了整個電容陣列的佈局面積大小。我們的主要目標就是在擺置的同時考慮減少繞線通道寬度和電容精確性。為了實現某些精準的電路功能，許多類比電路會使用任意比例(非整數)之電容，而在電容陣列佈局中，每一組任意比例之電容都至少需要有兩個電容是相鄰的，我們稱它為鄰接限制。除此之外在某些應用考量下，我們會希望電容陣列擺置的結果是正方形，此時可以額外加入空白電容以達到目的，雖然空白電容本身沒有不匹配的問題，但是它們的位置還是會影響到整體電容的不匹配。在這篇論文中，我們發表了配對序列表示法並且應用模擬退火法來建立一個共質心的擺置結果，並且同時考量了佈局面積的最小化和鄰接限制。

The key performance of many analog integrated circuits (ICs) is directly related to the accuracy of capacitance ratios. Nevertheless, systematic and random mismatches will affect the accuracy of the capacitance ratios. Although several studies have been proposed to consider mismatches in capacitor array placement, they did not consider routing problems. In this paper, the issue about routing for capacitor arrays is discussed, which includes routing area reduction in capacitor arrays. By considering mismatches and routing simultaneously in the phase of placement, the routing-induced problems which may cause unwanted effects to deteriorate analog layout quality can be prevented. To achieve precise circuit functions, many analog integrated circuits further employ non-integer-ratio capacitors. The layout of these capacitors can be implemented by non-unit capacitors and each non-unit capacitor must occupy the area of two adjacent unit capacitors, which is considered as adjacency constraint. A feasible placement for non-integer-ratio capacitors should meet the adjacency constraint. Besides, to make the placement more like a square, some dummy unit capacitors can be included in the placement. Although dummy unit capacitors do not induce mismatches, they indeed affect the mismatches of other capacitors if their locations are exchanged with others. To deal with the capacitor placement problem considering above requirements, we propose the pair-sequence representation and a simulated annealing based approach to construct a common-centroid placement which minimizes total layout area and satisfies the adjacency constraint simultaneously.

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