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研究生：	吳冠學 Wu, Kuan-Hsueh
論文名稱：	可延展性多執行緒處理器分析與研究 A Scalable Multi-Threaded processor analysis and research
指導教授：	周哲民 Jou, Jer-Min
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	中文
論文頁數：	71
中文關鍵詞：	可延展性、多執行緒、多核心
外文關鍵詞：	MPSOC, Multi-Threaded, SPARC
相關次數：	點閱：69 下載：1
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現今處理器為了達到更高的處理效能，多處理器系統單晶片已成了新一代SoC的主流設計趨勢。所謂多處理器系統單晶片(MPSoC)就是在SoC的架構下，放入多顆處理核心，來達到增加整體效能。多處理核心的發展主要是來自於以往單處理核心架構已經發展到接近極限，如：Deep-pipeline、Superscalar、VLIW、HyperThread等技術，造成處理器的設計變的極度複雜，而隨之而來的就是功率消耗、訊號延遲等問題，所以近期的處理器設計趨勢不在強調運作時脈，而是針對多核心的發展。
本論文中將藉由SUN公司在2006年所開放的OpenSPARC T1多核心多執行緒處理器的open source RTL code，來研究與分析多核心多執行緒處理器平台的內部運作為何具有極高的處理效能。OpenSPARC T1處理器為一個8核心，每個核心可執行4個執行緒，最多整個OpenSPARC T1處理器平台共可同時支援32個執行緒的執行。本論文將透過開放的RTL code去加以深入研究內部各個功能單元的多執行緒運作特性及機制，最後並將開放的RTL code利用Synplify來合成，以加以分析整個OpenSPARC T1的hierarchy view與所合成出的面積大小。以了解整個設計在成本面積與效能所達成的平衡所在。

In this thesis, we use the open source RTL codes of OpenSPARC T1 multi-core and multi-threaded processor which were opened by SUN in 2006 to research and analyze why there is high performance on the multi-core and multi-thread processor platform. The OpenSPARC T1 processor is a highly integrated processor implemented the 64-bit SPARC V9 architecture and contains eight SPARC processing cores, which each have full hardware support for four threads. So the whole OpenSPARC T1 processor supports 32 threads by combining ideas form chip multiprocessor. We research the mechanism and characterization for function units of each processing core by tracing open source RTL code further. Finally we had synthesized the processing core by using Synplify tool for analyzing the hierarchy view and area sizes of hardware architecture and understood the trad-off between cost and performance of design concept.

摘  要	I
Abstract	II
第一章 緒論	1
   1.1 研究背景與動機	1
   1.2 研究目的	1
   1.3論文架構	1
第二章 背景與相關研究	2
   2.1 處理器平行化探討[05]	2
      2.1.1 指令平行化(ILP)	2
         2.1.1.1 管線(Pipeline)	2
         2.1.1.2 超級管線(SuperPipeline)	3
         2.1.1.3 VLIW	3
      2.1.2 執行緒平行化(TLP)	3
         2.1.2.1 Chip-Multithread (CMT)	4
         2.1.2.2 Simultaneous Multithreading (SMT)	4
         2.1.2.3 Chip Multi-Processors (CMP)	5
         2.1.2.4 叢集架構(Ｃluster architecture)	6
         2.1.2.5 CMT+CMP	8
      2.1.3 Context-Switch 機制	9
   2.2 SPARC發展歷史	10
   2.3 OpenSPARC T1 overview	11
      2.3.1 OpenSPARC T1架構	12
      2.3.2 OpenSPARC T1核心設計[3]	12
      2.3.3 OpenSPARC T1發展目標	13
      2.3.4 OpenSPARC T1硬體架構	14
         2.3.4.1 OpenSPARC T1 功能單元特性簡介	14
      2.3.5 OpenSPARC T1 Instruction Set Architecture [1]	16
         2.3.5.1 指令格式 (Instruction Formats)	16
         2.3.5.2 指令欄位 (Instruction Fields)	19
         2.3.5.3 指令類別 (Instruction Categories)	21
         2.3.5.4 SPARC V9 指令集 (SPARC V9 Instruction Set)	22
第三章 OpenSPARC T1 Core之系統架構	26
   3.1 SPARC Core Pipeline Structures overview	26
   3.2 指令擷取單元（Instruction Fetch Unit）	27
      3.2.1 指令擷取 ( Instruction Fetch)	28
      3.2.2 指令快取填充路徑 (I-Cache Fill Path)	29
      3.2.3 指令失誤路徑 (I-Cache Miss Path)	30
      3.2.4 指令暫存器與程式計數器 (Instruction Register and Program Counter Register)	31
      3.2.5 指令快取(Level 1 Instruction Cache)	32
      3.2.6 指令旁視緩衝區 (instruction translation look-aside buffer)	33
         3.2.6.1 記憶體階層動作	34
      3.2.7 整數窗形暫存器 (Windowed Integer Register File)	35
      3.2.8 指令反轉機制 (Instruction Rollback Mechanism)	37
   3.3 執行單元（Execution Unit）	39
      3.3.1執行控制邏輯單元 (Execution Control Logic，ECL)	40
      3.3.2 旁路邏輯單元 (Bypass Logic)	40
      3.3.3 位移單元 (Shifter Unit)	41
      3.3.4 算術與邏輯運算單元 (Arithmetic and Logic Unit，ALU)	41
      3.3.5 整數乘法與除法運算單元 (IMUL and IDIV)	42
   3.4 載入儲存單元 (Load Store Unit)	43
      3.4.1 載入儲存單元管線(LSU Pipeline)	43
      3.4.2 資料流(Data Flow)	43
      3.4.3 Level 1 Data-cache (D-cache)	44
      3.4.4 資料轉換旁視緩衝區 (Data Translation Look-aside Buffer)	44
      3.4.5 儲存緩衝區 (Store Buffer)	45
      3.4.6 載入失誤佇列(Load Miss Queue)	46
      3.4.7 資料填充佇列(Data Fill Queue)	46
      3.4.8 Processor to crossbar Interface Arbiter	47
      3.4.9 CPU-Cache Crossbar	47
         3.4.9.1 CPU-Cache Crossbar Overview	47
         3.4.9.2 Processor-Cache Crossbar (PCX) and Packet format	48
         3.4.9.3 Cache-Processor Crossbar (CPX) and Packet format	48
   3.5 浮點數前端運算單元（Float-Point Frontend Unit）	49
      3.5.1 浮點數暫存器組 (Floating-Point Register File，FRF)	49
      3.5.2 FFU控制邏輯單元 (FFU Control，FFU_CTL)	49
      3.5.3 FFU資料路徑 (FFU Data-Path，FFU_DP)	49
      3.5.4 FFU VIS	49
   3.6 Stream Processing Unit (SPU)	50
   3.7 記憶體管理單元( Memory Management Unit)	50
      3.7.1 Data Flow in MMU	51
      3.7.2 TLB結構	51
      3.7.3 Virtual Address Space layout	52
   3.8 Trap Logic Unit (TLU)	53
      3.8.1 TLU功能簡介	54
      3.8.2 Architecture Register in the Trap Logic Unit	54
      3.8.3 Trap Stack	56
第四章 OpenSPARC T1多執行緒系統環境	57
   4.1 執行緒轉換方針 (Thread Switch Policy)	57
   4.2 執行緒狀態 (Thread State)	60
   4.3 執行緒排程 (Thread Scheduling)	61
   4.4 執行緒轉換邏輯單元(Thread Switch Logic)	62
第五章 實驗結果與分析	64
   5.1 合成流程與環境	64
   5.2 合成結果	66
第六章 結論與未來展望	67
參考文獻	68
附錄	70
                                    

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校外：2008-08-26公開

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