| 研究生: |
鍾旗鴻 Chung, Chi-Hung |
|---|---|
| 論文名稱: |
同時多執行緒處理器之研究與分析 Study and Anylsis of A Simultaneous Multithreaded Processor |
| 指導教授: |
周哲民
Jou, Jer-Min |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2010 |
| 畢業學年度: | 98 |
| 語文別: | 中文 |
| 論文頁數: | 72 |
| 中文關鍵詞: | 處理器 、模擬器 、同步多執行緒 |
| 外文關鍵詞: | Processor, Simulator, Simultaneous Multithreaded |
| 相關次數: | 點閱:91 下載:1 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
在系統晶片(Soc)的時代,特殊應用處理器是市場中重要的一環,在設計處理器為了具有好的效能以及短時間上市(Time to market)。 我們需要模型化處理器架構,立即性的探索和評估適合的處理器架構。通常架構的模擬技巧必須正確符合複雜處理器的行為以及產生出有效率的模擬器。
定義一個最好的處理器設計,設計者在探索廣泛的設計範圍,為了尋找適當的設計,設計者將會建構和使用模擬器,愈精簡的模型,建構時間愈短,可在短時間內,開發出較多的設計,並允許研究者快速評估新的設計,有效評價設計的內容,在廣泛評估中發展出淺明易懂的微架構。
同步多執行緒處理器相較於超純量處理器,並用了指令層級和執行緒層級的平行化,提高了硬體資源的使用率。我們使用Alpha 21164超純量處理器做為基礎,它具有8級的管線化之超純量架構,我們會研究與分析如何延展成8個執行緒的同步多執行緒處理器架構。
在此論文中,我們使用C/C++語言做為模型化同步多執行緒處理器的開發語言,我們會解釋設計同步多執行緒處理器的考量與應用,模擬結果則具備Cycle-Accurate特性,並能提供效能評價,給硬體或軟體設計者一個良好的參考。
In the system on chip (Soc) the time, the application-specific processor is an important part of the market. In designing a processor, in order to have a good performance and shorten the time-to-market. We need a modeling framework to rapidly explore and evaluate a candidate processor.
To identify the best processor designs, designers explore a vast design space. To assess the quality of candidate designs, designers construct and use simulators. Short model construction times allow more ideas to be explored in less time. This also allows researchers to evaluate new design ideas faster, to efficiently evaluate ideas in the context of many designs and perhaps develop a more fundamental understanding of micro-architecture due to these broader evaluations.
Simultaneous Multithreading processor compare to the superscalar processor is using the instruction level (ILP) and the thread level parallelism (TLP) the resources utilization ratio, we use the Alpha21164 superscalar processor for the overhead construction design foundation, it has 8-level pipelines of superscalar processor, we will expand 8 thread SMT overhead construction.
In this thesis, we apply the C/C++ language to study and anylsis a popular Simultaneous Multithreading processor. We also explain how to design a Simultaneous Multithreading processor. The generated simulator is a cycle-accurate simulator that can provide performance metric. It can offer both hardware and software developers a good reference.
[1] Robert A. Iannucci, Guang R. Gao, Robert H. Halstead, JR. Burton Smith.” Multithreaded Computer Architecture, A summary of the State of the Art”. Kluwer Academic Publishers, 1994.
[2] D.M. Tullsen, S.J. Eggers, and H.M. Simultaneous Multithreading: Maximizing On-Chip Parallelism, Levy, In 22nd Annual International Symposium on Computer Architecture, June, 1995
[3] Smith, J. E., and Sohi, G. The Microarchitecture of Superscalar Processors. Proceedings of the IEEE, vol. 83, pp 1609-1624, Dec 1995.
[4] D.M. Tullsen, S.J. Eggers, J.S. Emer, H.M. Levy, J.L. Lo, and R.L. Stamm. Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, In 23rd Annual International Symposium on Computer Architecture, May, 1996
[5] Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, and Dean M. Tullsen. Converting Thread-Level Parallelism into Instruction-Level Parallelism via Simultaneous Multithreading. ACM Transactions on Computer Systems, pp. 322-354, August 1997
[6] Deborah T. Marr, Frank Binns, David L. Hill, Glenn Hinton, David A. Koufaty, J. Alan Miller, Michael Upton. “Hyper-Threading Technology Architecture and Microarchitecture”. Intel Technology Journal Q1, 2002.
[7] John L. Hennessy and David A. Patterson. Computer Architecture: A Quantitative Approach, Third Edition. Morgan Kaufmann Publishers. 2002.
[8] http://www.rit.edu/~meseec/eecc722-fall2002/
[9] Wei Qin and , Modeling and Description of Embedded Processors for the Development of Software Tools, Ph.D Thesis, Princeton University.
[10] [WQ2003] Wei Qin and S. Malik. Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation, IEEE/ACM Design Automation and Test in Europe, March 2003, pp. 556-561.
[11] "Alpha 21264/EV67 Microprocessor Hardware Reference Manual," Compaq Computer Corporation, Product #DS-0028B-TE, 2000
[12] D. A. Patterson and J. L. Hennessy, "Computer Atchitecture a Quantitative Approach", Third Edition, Morgan Kaufmann Publisher, 2003
[13] Pees, Stefan, Modeling Embedded Processors and Generating Fast Simulators Using the Machine Description Language LISA, 2002
[14] K.Sanjeevan ,Toni Juan and Juan Jose Navarro."Single And Multiple Branch Prediction Strategies A Survey",August 1, 2000
[15] J. E. Smith. A study of branch prediction strategies. In: Proc. Of the 8th ISCA, 1981
[16] S.Pan, K.So, and J.Rahmeh. Improving the accuracy of dynamic branch prediction using branch correlation. In: Proc. of ASPLOS V, 1992
[17] S. McFarling. Combining branch predictors. TN 36, Digital Western Research Lab., 1993
[18] S. Hily, A. Seznec. Contention on 2nd level cache may limit the effectiveness of simultaneous multithreading , IRISA Report No 1086, 1997
[19] S. Hily, A. Seznec. Standard memory hierarchy does not fit simultaneous multithreading. In: Proc. Of MTEAC'98 Workshop, 1998
[20] D. Tullsen, J.Lo, S.Eggers, and H.Levy. Supporting fine-grained synchronization on a simultaneous multithreading processor. Technical Report CS98-587, UCSD, 1998
[21] Smith. B.J. The architecture of HEP. In Parallel MIMD Computation: HEP Supercomputer and Its Applications, J.S.Kowalik, Ed. MIT Press. Cambridge, MA, 1985.41-55
[22] Halstead R.H. and Fujita .T. MASA: A multithreaded processor architecture for parallel symbolic computing. In: Proc. of 15th International Symposium on Computer Architecture(Honolulu, HI), 1988. 443-451
[23] Alverson R., Callahan D., Cummings D., Koblenz B., Porterfield A. and Smith B. The Tera computer system.In: Proc. of International Conference on Supercomputing, 1990. 1-6
[24] Agarwal A., Bianchini R., Chaiken D., et al. The MIT Alewife machine: architecture and performance. In:Proc. of the 22th Annual International Symposium on Computer Architecture, 1995. 2-13
[25] Hammond .L., Hubbert B., et al. The Stanford Hydra CMP, IEEE Micro, 2000, 20(2):71-84.
[26] Diefendorff K. Power4 focus on memory bandwidth, Microprocessor Report, 1999.11-17
[27] Tremblay M. MAJC: Architecture for the new millennium, In: Proc. of the 11th Hot Chips, 1999. 275-288
[28] David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R.Eaton, Qudus B. Olaniran, and Wen-mei W. Hwu, Integrated Predicated and Speculative Execution in the IMPACT EPIC Archtecture. Proceedings of the 25th International Symposium on Computer Architecture, July, 1998
[29] Jurij Silc,Borut Robic and Theo Ungerer,”processor architecture form data flow to superscalar and beyond”,1999
[30] Matthew R. Guthaus, Jeffrey S. Ringenberg, Dan Ernst,Todd M. Austin, Trevor Mudge, Richard B. Brown.”MiBench: A free, commercially representative embedded benchmark suite”, IEEE 4th Annual Workshop on Workload Characterization, Austin, TX, December 2001.
[31] 楊宏偉, 同時多執行緒處理器之設計與模擬,國立成功大學電機工程學系, 碩士論文, 2005.
[32] 郭瑞宏, 以運算狀態機模型設計超純量處理器之模擬器,國立成功大學電機工程學系, 碩士論文, 2004.
[33] http://pascal.eng.uci.edu/Taiwan%20talk /talk_partI.pps [slice 16/24]
校內:2011-02-08公開