隨著物聯網的發展愈來愈完善，其中所需要的可攜式裝置數量也愈來愈多，而為了增加其電池壽命，提高內部微處理器的能量效益成為相當重要的發展方向。而在先進製程中的電晶體消耗相當大的漏電流，使得一般的微處理器在待機狀態時仍會消耗較多能量，因此不較符合常關式物聯網的需求。能應用在物聯網中的裝置需要具有待機能量消耗低的特性，而且內部記憶體要能夠快速儲存和回復資料才能維持一定效能。為了滿足該裝置的需求，近年來提出使用非揮發電源閘控架構的微處理器，而該架構主要的概念是利用其非揮發記憶體的特性，可以滿足物聯網的需求。由一般的靜態隨機存取記憶體以及新興記憶體結合出的新型記憶體能夠符合其架構的記憶體需求，其為非揮發性靜態隨機存取記憶體。本論文以180奈米製程設計，且提出能藉由在低電壓模式下備份資料來提高儲存能量效益的非揮發性靜態隨機存取記憶體，藉由記憶體內部所設計的非揮發性記憶體寫入加強控制器以及內建的自動中斷充電機制來達到降低非必要能量消耗，進而達到增加儲存能量效益的目的，和相關文獻相比，在儲存時間以及降低儲存能量比例的部分，本論文所提出的非揮發性靜態隨機存取記憶體在各部分均有一定的優勢。

As the Internet of Things (IoT) has evolved, the portable devices used in IoT also become more popular. To increase the battery lifetime of portable devices, raising energy efficiency of embedded microprocessors becomes an important issue. Transistors in advanced process consume significant amount of leakage current. General microprocessors thus fabricated still consume large amount of energy in standby mode. Therefore, they are less suitable for needs of normally-off IoT devices. An acceptable device shall have the characteristics of low standby energy consumption, and the memory inside needs to store/restore data quickly to maintain performance. To satisfy the demand of the devices, the microprocessor using nonvolatile power-gating architecture emerges in recent years. The major concept is to utilization the characteristics of nonvolatile memory. A new type of memory named as nonvolatile static random access memory (NVSRAM), that combines SRAM and emerging memory together, can satisfy the demands of the architectures. In the thesis, we propose to further raise store-energy efficiency of NVSRAM when backing up data in low-voltage mode. With the proposed write enhancement controller along with charging path auto-cutoff mechanism, the NVSRAM can reduce unnecessary energy dissipation to achieve the objective of increasing store-energy efficiency. When compared with other related work, the proposed design using 180nm CMOS technology process has advantages in store time and store energy efficiency.

參考文獻
[1] Statista Research Department, “2016. Internet of Things - number of connected devices worldwide 2015-2025.,” 2016. https://www.statista.com/statistics/471264/iot-number-of-connected-devices-worldwide/ (accessed Nov. 27, 2016).
[2] J. Gubbi, R. Buyya, S. Marusic, and M. Palaniswami, “Internet of Things (IoT):A vision, architectural elements, and future directions,” Future Generation Computer Systems, vol. 29, no. 7, pp. 1645–1660, 2013.
[3] T. Adegbija, A. Rogacs, C. Patel, and A. Gordon-Ross, “Microprocessor optimizations for the internet of things: A survey,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and System., vol. 37, no. 1, pp. 7–20, 2018.
[4] S. Popli, R. K. Jha, and S. Jain, “A Survey on Energy Efficient Narrowband Internet of Things (NBIoT): Architecture, Application and Challenges,” IEEE Access, vol. 7, pp. 16739–16776, 2019.
[5] M. H. Abu-Rahma and M. Anis, Nanometer Variation-Tolerant SRAM. Springer, 2013.
[6] N. Verma, “Analysis towards minimization of total SRAM energy over active and idle operating modes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 9, pp. 1695-1703, 2011.
[7] C. R. Huang, K. L. Wu, C. H. Wu, and L. Y. Chiou, “Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme,” in Proceeding of IEEE International Symposium on Circuits and Systems, vol. 2018-May, 2018, pp. 2018–2021.
[8] Y. Shuto, S. Yamamoto, and S. Sugahara, “New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM,” in Proceeding of IEEE International Conference on Microelectronic Test Structures, vol. 2016-May, 2016, pp. 136–141.
[9] Z. Wang, Y. Liu, A. Lee, F. Su, C. P. Lo, Z. Yuan, J. Li, C. C. Lin, W. H. Chen, H. Y. Chiu, W. E. Lin, Y. C. King ; C. J. Lin, P. K. Amiri, K. L. Wang, M. F. Chang and H. Yang, “A 65-nm ReRAM-Enabled Nonvolatile Processor with Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed,” IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2769–2785, 2017.
[10] M. F. Chang and S. J. Shen, “A process variation tolerant embedded split-gate flash memory using pre-stable current sensing scheme,” IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 987–994, 2009.
[11] S. S. Sheu, K. H. Cheng, M. F. Chang, P. C. Chiang, W. P. Lin, H. Y. Lee, P. S. Chen, Y. S. Chen, T. Y. Wu, F. T. Chen, K. L. Su, M. J. Kao and M. J. Tsai, “Fast-write resistive RAM (RRAM) for embedded applications,” IEEE Design and Test of Computers, vol. 28, no. 1, pp. 64–71, 2011.
[12] Y. Xie and Y. Zhao, “Emerging memory technologies,” IEEE Micro, vol. 39, no. 1, pp. 6–7, 2019.
[13] C. Wang, H. Wu, B. Gao, T. Zhang, Y. Yang, and H. Qian, “Conduction mechanisms, dynamics and stability in ReRAMs,” Microelectronic Engineering, vol. 187–188, pp. 121–133, 2018.
[14] A. Lee, M. F. Chang, C. C. Lin, C. F. Chen, M. S. Ho, C. C. Kuo, P. L. Tseng, S. S. Sheu and T. K. Ku, “RRAM-based 7T1R nonvolatile SRAM with 2x reduction in store energy and 94x reduction in restore energy for frequent-off instant-on applications,” in Proceeding of IEEE Symposium on VLSI Circuits, Digest Technical Papers, vol. 2015-Augus, 2015, pp. C76–C77.
[15] S. S. Sheu, C. C. Kuo, M. F. Chang, P. L. Tseng, C. S. Lin, M. C. Wang, C. H. Lin, W. P. Lin, T. K. Chien, S. H. Lee, S. C. Liu, H. Y. Lee, P. S. Chen, Y. S. Chen, C. C. Hsu, F. T. Chen, K. L. Su, T. K. Ku, M. J. Tsai and M. J. Kao, “A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application,” in Proceeding of 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013, pp. 245–248.
[16] P. F. Chiu, M. F. Chang, C. W. Wu, C. H. Chuang, S. S. Sheu, Y. S. Chen and M. J. Tsai, “Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with vertical-stacked resistive memory (memristor) devices for low power mobile applications,” IEEE Journal Solid-State Circuits, vol. 47, no. 6, pp. 1483–1496, 2012.
[17] T. K. Chien, L. Y. Chiou, Y. S. Tsou, S. S. Sheu, P. H. Wang, M. J. Tsai and C. I. Wu, “Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches,” in Proceeding of International Symposium on Low Power Electronics and Design (ISLPED), 2017.
[18] L. Bagheriye, S. Toofan, R. Saeidi, B. Zeinali, and F. Moradi, “A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA,” IEEE Transactions on Circuits and System II: Express Briefs, vol. 65, no. 11, pp. 1708–1712, 2018.
[19] Y. Shuto, S. Yamamoto, and S. Sugahara, “Analysis of static noise margin and power-gating efficiency of a new nonvolatile SRAM cell using pseudo-spin-MOSFETs,” in Proceeding of 2012 IEEE Silicon Nanoelectronic Workshop (SNW), vol. 1, 2012, pp. 3–6.
[20] K. Monga, A. Malhotra, N. Chaturvedi, and S. Gurunayaranan, “A Novel Low Power Non-Volatile SRAM Cell with Self Write Termination,” in Proceeding of 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2019, pp. 11–14.
[21] C. Dray, N. Badereddine, and C. Chanussot, “A 40nm low power SRAM retention circuit with PVT-aware self-refreshing virtual VDD regulation,” in Proceeding of 2010 IEEE International Memory Workshop (IMW), 2010, pp. 11–14.
[22] M. Roy and Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proceedings of IEEE, vol. 91, no. 2, p. 303, 2003.
[23] Z. Shi, D. Zhou, K. Qiu, and J. Shu, “Leveraging energy cycle regularity to predict adaptive mode for non-volatile processors,” in Proceeding of International Conference on Application-Specific Systems, Architectures and Processors, vol. 2019-July, 2019, pp. 189–196.
[24] S. Yamamoto, Y. Shuto, and S. Sugahara, “Nonvolatile SRAM (NV-SRAM) using functional MOSFET merged with resistive switching devices,” in Proceeding of Custom Integrated Circuits Conference, 2009, pp. 531–534.
[25] K. S. Li, C. H. Ho, M. T. Lee, M. C. Chen, C. L. Hsu, J. M. Lu, C. H. Lin, C. C. Chen, B. W. Wu, Y. F. Hou, C. Yi. Lin, Y. J. Chen, T. Y. Lai, M. Y. Li, I. Yang, C. S. Wu, and F. L. Yang, “Utilizing Sub-5 nm sidewall electrode technology for atomic-scale resistive memory fabrication,” in Proceeding of Digest of Technical Papers – Symposium on VLSI Technology, 2014, pp. 210–211.