本篇論文提出一個低耗能低雜訊的類比前端放大電路的設計（AFE）。針對可攜式系統需要低功率的需求提出一個簡化版的微分差動儀表放大器，可以有效的降低功率和縮小晶片面積，並且在微分差動放大器中加入截波穩壓技術，可以有效的移除閃爍雜訊，達到低雜訊的特性，整體晶片為目前EEG、ECG通用類比前端放大電路中消耗功率非常低，晶片面積最小的著作。使用台積電0.18微米1P6M的製程。在Post simulation中供應電壓為1.8V，在工作頻率10kHz有效訊號頻寬10 kHz下，平均消耗功率16μW，共模雜訊抑制比(Common Mode Rejection Ratio, CMRR)達到140dB。整個晶片的核心面積為0.082 mm2。

In this paper, a low-power and low-noise CMOS analog front-end amplifier is presented in this work. An analog front-end amplifier circuit includes the instrumentation amplifier (IA), low-pass filter (LPF) and the gain stage. Required for portable systems demand, we propose a simplified chopper-stabilized differential difference instrumentation amplifier, it can effectively reduce the power and reduce the chip area. For the present EEG and ECG signal acquisition system, this work has the lowest power consumption and the smallest chip area. The circuit was prototyped in 0.18um CMOS process and consumes 16.0μW from a 1.8 V supply voltage. Simulation results show that CMRR is over 140dB. The core area of the test chip is 0.082 mm2.

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