現今的處理器通常會使用虛擬記憶體以獲得更大的記憶體容量及讓程式共享記憶體。為了減少存取主記憶體的次數，處理器的記憶體系統會整合轉譯查詢緩衝器(TLB)以增進位址轉譯的效能。在測試這些記憶體系統，傳統上會使用內建式自我測試或是掃描鏈等可測試設計技術。然而，這些在電路中額外增加的測試電路將會影響TLB本身的效能，也會增加電路的面積負擔。因此，一種無傷害的測試方式可解決TLB的測試問題，稱為軟體測試方法。這種方法使用處理器本身的資源來測試TLB，因而不需要增加任何的測試電路或修改處理器的設計即可達到良好的測試效果。

本論文中，我們針對一個相容於ARM的32位元處理器中的直接對映式TLB提出一個軟體測試方法。此處理器採用哈佛架構，因此會分成DTLB和ITLB。在TLB的記憶體元件，我們轉換用於Memory BIST的March演算法為指令的形式來測試，可完整測到DTLB常見的記憶體錯誤。在測試TLB的邏輯元件部分，我們針對TLB的暫存器轉移階層(RTL)描述來分類元件，並且根據各元件的架構特性來發展測試程式。我們所提出的測試方案在DTLB的邏輯部分可達到97.29%的錯誤涵蓋率，ITLB的邏輯部分可達到97.88%的錯誤涵蓋率。

Modern processors usually use virtual memory technique. This scheme allows programs to own memory space larger than the physical memory, and lets processes share files and address space easily. In order to reduce the number of accesses to the main memory, the memory system of a processor usually integrates a translation look-aside buffer (TLB) to improve performance of address translation. Conventionally design-for-testability (DFT) techniques, such as scan chain and built-in self-test (BIST) mechanisms, are used for testing the TLB. However, the insertion of test circuits could cause performance degradation and area overhead. Hence, a software-based test methodology which uses processor resources to test the TLB can be used for high performance consideration. In this thesis, we propose a software-based test methodology for the direct-mapped TLB of an ARM-based processor. We translate March algorithm into executable instructions to test the memory part of the TLB. For the logic part of the TLB, we consider the register transfer level description of the components to develop the test programs. Based on the developed test programs, the logic part of the DTLB can achieve 97.29% fault coverage and the logic part of the ITLB can achieve 97.88% fault coverage while the memory part of the DTLB can achieve 100% fault coverage.

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