現今高階合成(High-Level Synthesis)演算法主要在單一時脈頻率下合成單一取樣率之電路，在本論文中我們提出一個基於生產量驅動的高階合成演算法，可將多重取樣率(Multiple Sampling Rates)之複雜電路合成出擁有多重時脈頻率(Multiple Clock Domains)的電路，演算法首先分析電路中的每個運算區塊並探索出可行的時脈頻率，目的是找出每個區塊盡可能越低的時脈頻率並且達到使用者給定之生產量要求，進而降低電路的功率消耗。最後演算法在區塊間插入最佳化深度之緩衝器來完成電路，實驗數據顯示使用我們方法產生之電路相比於傳統高階合成方法產生之電路可降低87%的功率消耗。

Current High-level synthesis (HLS) algorithms mainly synthesize components with single sampling rate in a single clock domain. In this work we present a novel throughput driven HLS algorithm that can synthesize a complex hardware block with multiple sampling rates into a design with multiple clock domains. The algorithm first profiles components in a complex hardware block and explores possible clock domains of each component. The goal is to identify the lowest possible clock rate of each component that meets the throughput constraint, thereby yielding the lowest power consumption. The buffers with optimal depth are then inserted between components to complete the design. Experimental results show that our approach achieved 87% power reduction compared to the traditional HLS approach.

[1] D. D. Gajski, N. D. Dutt, A. C.-H. Wu, and S. Y.-L. Lin, “High-Level Synthesis: Introduction to Chip and System Design,” Kluwer Academic Publishers, 1992.
[2] Xilinx Vivado HLS (www.xilinx.com/products/design-tools/vivado/)
[3] NEC CyberWorkBench (www.cyberworkbench.com)
[4] Synopsys Synphony (www.synopsys.com/Systems/BlockDesign/HLS/Pages/SynphonyC-Compiler.aspx)
[5] E. Lee and D. Messerschmitt, “Synchronous Data Flow,” Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, 1987.
[6] B. C. Schafer, “Automatic Partitioning of Behavioral Descriptions for High-Level Synthesis with Multiple Internal Throughputs,” in Electronic System Level Synthesis Conference (ESLsyn), pp. 1-6, 2013.
[7] S. Li, Y. Liu, X.S. Hu, X. He, Y. Zhang, P. Zhang and H. Yang, “Optimal Partition with Block-Level Parallelization in C-to-RTL Synthesis for Streaming Applications,” in Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 225-230, 2013.
[8] J. Cong, M. Huang, B. Liu, P. Zhang and Y. Zou, “Combing Module Selection and Replication for Throughput-Driven Streaming Programs,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1018-1023, 2012.
[9] J. Zhu, I. Sander and A. Jantsch, “Energy Efficient Streaming Applications with Guaranteed Throughput on MPSoCs,” in International Conference on Embedded Software (EMSOFT), pp. 119-128, 2008.