可繞度在當今的類比及混合電路設計成為一個很重要的議題，若沒有在擺置階段考量可繞度問題，會導致繞線路徑迂迴並生成較長的線長，造成不必要的寄生效應，此外，也會使得金屬層過於擁擠，甚至最終導致繞線失敗。因為許多先前關於可繞度為導向之類比電路擺置的研究都將電晶體視為障礙物，因此這些研究在擺置電晶體時將會保留通道來預留繞線空間。然而，為了進一步節省繞線面積，許多實際業界的產品是允許繞線橫跨過電晶體。基於這樣的需求，我們應用一個以可繞度為導向並基於模擬退火法的演算法來處理電晶體的擺置。由於模擬退火法本來就是一個相當耗時的演算法，當其還需要可繞度時會使得其速度更加緩慢。為了解決這個問題，本篇論文提出了一個兩階段式的花費評估方法來達到加速的目的。為了能夠有效估量可繞度的花費，本篇論文使用了一個能調整繞線順序之簡易且高效的繞線演算法。除此之外，在決定電晶體擺置時，本篇論文還提出了一個基於群集演算法的方法來估量偏壓訊號的繞線資源使用，這些訊號通常有著高度的敏感度並通常在類比電路繞線時有最優先的順序。實驗結果展示了我們的方法能有效並有效率地提升可繞度，並且還能同時最小化空白區域來滿足所有使用者自訂的限制。

Routability has become a more important issue in the modern analog and mixed-signal circuit design. If routability is not considered during the device placement stage, it may cause routing detour and induce longer wirelength, which generates unnecessary parasitic effects. Moreover, it will lead to higher routing congestion in metal layers or even result in routing failure. Since most of previous researches treat the devices as obstacles, they usually keep routing channels between devices in order reserve routing resource in the placement phase. However, in order to save layout areas, some practical analog circuits allow nets across devices in industry. Based on this requirement, we apply a routability-driven SA based algorithm to handle device placement. Since the SA based algorithm is time consuming especially when routability is considered, this thesis proposes a two-stage cost evaluation procedure to speed up runtime. To evaluate routability of a placement efficiently, this thesis applies a simple and efficient routing algorithm with a better net ordering. Besides, we apply a clustering-based method to evaluate the cost for bias signals which have the highest sensitivity and routing priority in analog circuits during placement. The experimental results show our methodology is effective and efficient to increase routability while minimizing white space and satisfying all user-specified placement constraints.

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