在本論文中，首先提出兩個節省功率的技術，以降低一般CMOS影像感測器中使用位移暫存器架構製作的讀出控制電路的動態及靜態功率消耗。為了降低動態的消耗功率，我們設計了一個新式的時脈閘控單元電路並將這個元件放置於分散式時脈樹中每個反相器前。透過時脈閘控單元控制時脈的供應，位移暫存器中沒有工作的正反器將被關閉。此外，這些時脈閘控單元的控制訊號可透過位移暫存器自身產生的內部訊號作控制而不需額外的控制訊號。經由分析與模擬得到動態的功率消耗與位移暫存器中D型正反器的數目呈對數比例。當讀出一個像素陣列大於或等於128×128，可節省超過90%的動態消耗功率。漏電流是靜態功率消耗的主因。我們結合電晶體疊接技巧設計了一個新型的低漏電流D型正反器以降低超過80%的靜態消耗功率。
第二，針對一般CMOS影像感測器中使用快閃式類比數位轉換器，我們提出一個摺疊技術來降低解碼器部分的電路複雜度。原本k個位元的解碼器經過摺疊形成兩個子解碼器，分別處理k/2個高位元與k/2個低位元的解碼。每個子解碼器的輸入數目減少為原本數目的平分根。經由分析，對於不同架構的解碼器，可減少超過17%的硬體消耗及13%的時間延遲並同時提升抗泡沫引發雜訊的能力。我們利用0.18 μm CMOS製程實作了一個六位元的快閃式類比數位轉換器，面積為0.37 mm×0.35 mm。經由模擬，在十億分之一秒取樣速度下得到優值數為1.03 pJ/conversion-step並且最大泡沫引發雜訊會被限制在泡沫的個數內。
第三，針對數位式CMOS影像感測器的應用，我們提出了一個適應性取樣演算法並發展了一個可同時具備高動態範圍與近對數響應的數位式CMOS影像感測器。像素層級的類比數位轉換利用結合一個比較器與一個四位元的靜態記憶體來實現。這個感測器可提供線性與對數的響應模式。在不同的響應模式下，透過提出的時序控制機制，每個像素對應的八位元數位輸出值可被決定並取得，而像素層級的訊號處理特性可降低整體電路的功率與硬體消耗。新式的數位像素感測器面積約為15.8 μm×15.8 μm 而填滿因子為21%。模擬結果得到新式的數位像素感測器可正常運作而可達到的動態範圍在線性與對數響應模式中分別為48 dB 與 114 dB。

In this dissertation, first, two power saving techniques are proposed to reduce both dynamic and static power consumption of shift-register-based readout control circuits in conventional CMOS image sensors. To reduce the power consumption in dynamic domain, a new clock gating control unit (CGCU) is designed and inserted in front of an inverter in the distributed clock tree. The CGCUs operate as pruners for disabling portions of the circuitry where flip-flops do not change state. Without using extra control signals, the signals generated by the shift register itself are utilized as the control signals of CGCUs. According to the analysis and simulations, the dynamic power dissipation is proportional to the logarithm of the number of D flip-flops. More than 90% of dynamic power saving is achieved when reading out a frame with size of equal to or larger than 128×128. The static power dissipation is mainly from the leakage current. A low leakage D filp-flop by adopting the stack technique is designed. Simulations show that more than 80% of static power saving is achieved.
Second, a folding technique is proposed to reduce the decoder circuit complexity of a flash ADC in the conventional CMOS image sensors. After folding, a k-bit decoder is replaced with two sub-decoders. The decoding of the upper k/2 bits and the lower k/2 bits can be accomplished respectively. Consequently, the number of inputs to the decoder is reduced to the square root of the original. Analytic results show that for different decoder structures, more than 17% of hardware and 13% of time delay can be saved. Moreover, the tolerance of bubble induced errors is enhanced. A 6-bit flash ADC has been implemented in 0.18-μm CMOS that occupies 0.37mm×0.35mm active area. Simulations show that the figure-of-merit number is as low as 1.03 pJ/conversion-step at 1G Sample/s and the maximum bubble induced error is limited to the number of bubbles.
Third, we propose an adaptive-sampling algorithm and develop a digital CMOS pixel sensor which has features of wide dynamic range and approximated-logarithmic response. In this new architecture the pixel-level analog-to-digital conversion is realized by employing a comparator combined with a 4-bit in-pixel static memory. Under different response modes, the corresponding 8 bits digitalized value of a pixel can be obtained by applying the proposed timing control schemes. Since the signal processing is accomplished at pixel-level, both power consumption and hardware cost are lowered. The designed pixel occupies an area of 15.8 μm×15.8 μm with a fill factor of 21%. Simulation results validate the effectiveness of the proposed DPS and the achievable dynamic range is 48 dB in linear response mode and 114 dB in logarithmic response mode respectively.

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