| 研究生: |
黃冠霖 Huang, Kuan-Lin |
|---|---|
| 論文名稱: |
具有放大器共享且可調動態範圍的高通三角積分調變器 An Op-amp Sharing Based Wide Dynamic-range High-pass Sigma-delta Modulator with Programmable Feed-forward Coefficients |
| 指導教授: |
李順裕
Lee, Shuenn-Yuh |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2019 |
| 畢業學年度: | 108 |
| 語文別: | 中文 |
| 論文頁數: | 69 |
| 中文關鍵詞: | 動態範圍 、程式化前饋係數 、放大器共享技術 、高通三角積分調變器 |
| 外文關鍵詞: | high-pass sigma-delta modulator, programmable feed-forward coefficients, op-amp sharing, dynamic range |
| 相關次數: | 點閱:79 下載:3 |
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本論文為應用於心電訊號檢測系統中的三角積分調變器電路,在此提出一個具備放大器共享技術、可程式化動態範圍的高通三角積分調變器,電路設計目標為低功耗與高解析度,目的為達到長時間的檢測與人工智慧的辨識。
製程使用0.18μm 1P6M來實現一具有放大器共享且可調動態範圍的高通三角積分調變器,此高通三角積分調變器為三階前饋的架構,利用額外的電容及兩倍週期的時脈,調整高通濾波器的架構,令第二階及第三階的高通濾波器共用一個放大器,同時維持抑制雜訊的轉移函數,使放大器的個數減少,功耗大幅降低。而由於心電訊號的大小因人而異,因此,利用可程式化的前饋係數來控制三角積分調變器的動態範圍,可使不同振幅的心電訊號,都能有良好的解析度。
量測結果顯示,加入了可程式的前饋係數之技術,動態範圍延伸了12 dB。此外,在供應電壓為1.2V的情況下,SFDR為69.5 dB,功率消耗僅為2.25μW,其規格與已知文獻中的高通三角積分調變器相比,皆有不錯的表現。
A high-pass sigma-delta modulator (HPSDM) using op-amp sharing and programmable feed-forward coefficients is presented for the electrocardiography (ECG) signal detection system. Since the amplifier dominates the whole power consumption of the HPSDM, op-amp sharing is used to reduce the quantity of the amplifiers. Moreover, the amplitude of the ECG varies from person to person, hence the programmable feed-forward coefficients are used to adjust the dynamic range of HPSDM to obtain high resolution for different users. This technique was implemented using the 0.18 μm standard CMOS process, and the measurement results reveal the proposed HPSDM has the SNDR of 54.5 dB and the power of 2.25μW under a 1.2-V supply voltage to achieve the figure of merit of 12.96 pJ/conv. Wth the other setting, the proposed HPSDM has the SNDR of 64.8 dB and the power of 5.2μW under a 1.8-V supply voltage to achieve the figure of merit of 9.15 pJ/conv. Both of them extends the dynamic range of 12 dB according to the programmable feed-forward coefficients.
[1] World health organization. “Top 10 causes of death.”
https:// www.who.int/news-room/fact-sheets/detail/the-top-10-causes-of-death
[2] N. V. Helleputte, M. Konijnenburg, J. Pettine, D. W. Jee, H. K. Kim, A. Morgado, R. V. Wegberg, T. Torfs, R. Mohan, A. Breeschoten, H. d. Groot, C. V. Hoof, and R. F. Yazicioglu,"A 345μW multi-sensor biomedical SoC with bio-impedance, 3-channel ECG, motion artifact reduction, and integrated DSP," IEEE J. Solid-State Circuits, vol. 50, no. 1, pp. 230-244, Jan. 2015.
[3] R. Mohan, S. Hiseni, and W. A. Serdijn, "A highly linear, sigma-delta based, sub-Hz high-pass filtered ExG readout system," Proc. IEEE International Symposium on Circuits and Systems, Beijing, China, May 19-23, 2013
[4] L. S. Y. Wong, S. Hossain, A. Ta, J. Edvinsson, D. H. Rivas, and H. Nääs, "A very low-power CMOS mixed-signal IC for implantable pacemaker applications" IEEE J. Solid-State Circuits, vol. 39, no.12, pp. 2446-2456, Dec. 2004.
[5] J. G. Webster, Medical Instrumentation, application and design, 4th ed. NJ: Wiley, 2008
[6] C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization," Proc. IEEE, vol. 84, no. 11, pp. 1854-1614, Nov. 1996.
[7] S. Y. Lee, Y. C. Su, M. C. Liang, J. H. Hong, C. H. Hsieh, C. M. Yang, Y. Y. Chen, H. Y. Lai, J. W. Lin, and Q. Fang, "A programmable implantable micro-stimulator SoC with wireless telemetry: Application in closed-loop endocardial stimulation for cardiac pacemaker," in Proc. IEEE Solid State Circuits Conf., Feb. 2011, pp. 44-45.
[8] S. Y. Lee, J. H. Hong, C. H. Hsieh, M. C. Liang, S. Y. C. Chien, and K. H. Lin,"Low-power wireless ECG acquisition and classification system for body sensor networks," IEEE J. Biomed. Health Informat., vol. 19, no. 1, pp. 236-246, Jan. 2015.
[9] J. M. de la. Rosa, R. del. Rio, Sigma-Delta Converters: Practical Design Guide. Chichester: Wiley, 2018
[10] B. E. Boser and B. A. Wooley, "The design of sigma-delta modulation analog-to-digital converters," IEEE J. Solid-State Circuits. Vol. 23. no. 6. pp. 1298-1308. Dec. 1988.
[11] P. Malcovati, S. Brigati, F. Franncesconi, F. Maloberti, and A. Baschirotto, “Behavioral modeling of switched-capacitor sigma-delta modulators,” IEEE Trans. Circuits Syst. 1, Fundam. Theory Appl., vol.50, no. 3, pp. 352-364, Mar. 2003.
[12] S. Y. Lee, C. Y. Chen, J. H. Hong, R. G. Chang, and M. P. H. Lin, “Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist,” Microelectron. J., vol 42, no. 2, pp. 347-357, Jan. 2011.
[13] K. Chandrashekar and B. Bakkaloglu, “A 10b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 19, no. 9, pp. 1610-1616, Sep. 2011.
[14] D. Kanemoto, T. Ido, and K. Taniguchi, “A novel third order delta sigma modulator with one opamp shared among three integrator stages”, IEICE Electron. Express, vol. 5, no. 24, pp. 1088-1092, (2008)
[15] D. Kanemoto, T. Ido, and K. Taniguchi, “A 7.5mW 101dB SNR low-power high-performance audio delta-sigma modulator utilizing opamp sharing technique,” IEEE International SoC Design Conference 2011, pp. 66-69, Nov. 2011.
[16] R. G. Chang, C. Y. Chen, J. H. Hong, and S. Y. Lee, “Wide dynamic-range sigma-delta modulator with adaptive feed-forward coefficients,” IET Circuits, Devices Syst., vol. 4, no. 2, pp. 99-112, Mar. 2010.
[17] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2005.
[18] V. T. Nguyen, P. Loumeau, and J. F. Naviner, “VHDL-AMS behavioral modeling and simulation of high-pass delta-sigma modulator,” Behavioral Modeling and Simulation Workshop, 2005, pp. 106-111.
[19] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-sigma data converters, in Theory, Design and Simulation. (Piscataway, NJ:IEEE Press, 1997).
[20] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
[21] A. Noman, M. Dessouky, and K. Sharaf, “A dual phase SC CMFB circuit for double sampling modulators,” IEEE 2003 46th Midwest Symposium on Circuits and Systems, pp. 287-290, Dec. 2003.
[22] C. Liu, S. Chang, G. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April, 2010.
[23] B. Wicht, T. Nirschl, and D. S. Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, July, 2004.
[24] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 10-bit charge-redistribution ADC consuming 1.9uw at 1MS/s,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, 2010.
[25] Linear Technology. LT1761 Series 100mA, Low Noise, LDO Micropower Regulators in TSOT-23. [Online]. Available
https://www.analog.com/media/en/technical-documentation/data-sheets/1761sff.pdf
[26] R. Muller, H.-P. Le, W. Li, P. Ledochowitsch, S. Gambini, T. Björninen, A. Koralek, J. M. Carmena, M. M. Maharbiz, E. Alon, and J. M. Rabaey, “A minimally invasive 64-channel wireless μECoG implant,” IEEE J. Solid-State Circuit, vol. 50, no. 1, pp.344-359, Jan. 2015.
[27] R. Mohan, S. Zaliasl, G. G. E. Gielen, C. Van Hoof, R. F. Yazicioglu, and N. Van Helleputte, “A 0.6-V, 0.015-mm2, time-based ECG readout for ambulatory applications in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 298–308, Jan. 2017.
[28] S. Rout and W. Serdijn, "High-pass ∆∑ converter design using a state-space approach and its application to cardiac signal acquisition. " IEEE Transactions on Biomedical Circuits and Systems, vol. 12, no. 3, pp.483-494, Jun. 2018.
[29] Y. Chae and G. Han, "Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator," IEEE J. Solid-State Circuits, vol. 44, no.2, pp. 458-472, Feb. 2009.
[30] A. F. Yeknami, F. Qazi, and A. Alvandpour, "Low-power DT ∆∑ modulators using SC passive filters in 65 nm CMOS," IEEE Trans. Circuits Syst. I, vol. 61, no. 2, pp. 358-370, Feb. 2014.
[31] R. Schreier and G. C. Temes, “Understanding delta-sigma data converters.” Piscataway, NJ:IEEE Press, 2005.