本論文提出了一個應用於高速類比數位轉換器之反頻疊失真切換式電容低通濾波器。論文中，除了使用六階的橢圓型濾波器來降低運算放大器的數量以及功率消耗之外，亦採用串接電路架構來降低對元件變化的敏感度。
我們首先使用SWITCAP來針對電路的非理想效應進行分析與模擬，運算放大器的非理想性，諸如有限低頻增益、有限頻寬及有限迴轉率等對整體濾波器效能造成影響之因素均納入考量。濾波器設計技巧，如極零點配對與排序、適應性動態範圍調整與最佳電容大小的選擇亦涵蓋在整體電路設計之中。模擬結果顯示濾波器在4.72 MHz導通頻寬內能達到0 dB增益，而導通頻帶漣波能壓抑在1.31 dB之內，且截止頻率為8 MHz，其增益為 -53 dB。此低通濾波器以0.35 μm製程設計，由佈局圖顯示晶片整體面積大約為1.8 mm × 2.1 mm。

In this thesis, a switched-capacitor (SC) lowpass filter dedicated to high speed ADC applications is proposed. The six-order elliptic filter is selected to reduce the number of operational amplifiers (opamps) and power consumption. The cascade architecture is adopted which has low sensitivity to component tolerances and is efficient in its use of high-order filter circuits.
The non-ideal factors within a SC filter are analyzed and modeled using SWITCAP in prior to the transistor-level design. Techniques such as zeros/poles pairing and ordering, dynamic range scaling and optimal capacitance assignment are adopted in the filter design. Simulation results show the overall filter achieves a gain of 0 dB in the passband within 4.72 MHz, with -1.31 dB of maximum passband ripple. The image rejection is under -53 dB at 8 MHz. The lowpass filter is designed with the TSMC 0.35-μm 2P4M process, and occupies an area of approximately 1.8 mm × 2.1 mm.

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