本篇論文的主要目的是設計一個基於小波轉換的語音增強系統演算法的硬體，並將其實現與驗證。論文內容主要分成小波包轉換與語音增強系統演算法實現兩部分：
在小波包轉換實現的部分，我們提出一個摺疊式小波包的分解架構，此架構不需額外的儲存單元便可以實現我們所需要的小波包轉換，在合成的部分，我們提出的架構需要一半音框長度的記憶體來儲存小波合成的係數，最後我們將小波包分解以及結合的架構整合在一起並與其他的架構做比較，證明我們的架構在面積上比其他的架構更為優秀。
在語音增強系統演算法的硬體實現的部分，我們使用兩種不同的處理方式來實現，一種是由小波包轉換完成後直接輸入語音增強系統來做運算，另一種是由記憶體輸入小波包係數來做運算，此兩種不同的處理方式分別稱為即時處理以及非即時處理，在效能的表現上，即時處理的架構擁有較好的執行時間而非即時處理的架構則擁有較小的面積，我們的實現方式是以 Verilog HDL 描述所提出的電路架構，並使用TSMC 0.18 um的技術合成，最後在 FPGA 上進行合成及佈局繞線後驗證。

In this thesis, we focus on the hardware implementation of a wavelet-based speech enhancement system and verify it. It consists of two parts: In the first part we proposed the architecture of analysis and synthesis wavelet packet transform. The folded architecture is used to implement the analysis lifting wavelet packet and not need extra memory unit to save the temporary coefficients. The architecture of synthesis wavelet packet transform needs extra memory that has half of frame length. Finally we combined the architecture of analysis and synthesis and compare with other architectures. It proves our architecture has smaller area.
In the second part we proposed two different processing types of speech enhancement system, named real time and non-real time processing respectively. The real time processing has the input from analysis wavelet transform and non-real time processing has the input from the memory. The real time processing has lower latency and the non-real time has smaller area. The proposed architectures are synthesized with TSMC 0.18 um technology. Finally we use ARM development platform to verify our architectures.

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