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研究生: 宋明翰
SUNG, MING-HAN
論文名稱: 5.5 GHz CMOS 電流再利用低雜訊放大器與主動式降頻吉伯特混頻器之設計
Design of a 5.5-GHz CMOS Current-Reuse Low-Noise Amplifier and Active Down-Conversion Gilbert Mixer
指導教授: 黃尊禧
Huang, Tzuen-Hsi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2026
畢業學年度: 114
語文別: 中文
論文頁數: 123
中文關鍵詞: C-BandWLAN低雜訊放大器混頻器
外文關鍵詞: C-Band, WLAN, Low-Noise Amplifier, Mixer
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  • 本論文設計應用於 IEEE 802.11a/ac WLAN 5 GHz 頻段之射頻接收機前端電路,包含 5.5 GHz 電流再利用低雜訊放大器及 5.5 GHz 主動式吉伯特降頻混頻器,皆採用 TSMC 0.18-μm CMOS 製程實現。
    低雜訊放大器採用電流再利用架構,結合共源級放大器及源極退化電感技術,在降低功率消耗的同時兼顧輸入匹配、高增益及低雜訊特性。混頻器則採用雙平衡式吉伯特架構,並結合 GM/ID 設計方法與負載線分析進行電晶體尺寸及偏壓最佳化,以提升設計效率與電路性能。此外,於轉導級導入多閘極電晶體線性化技術,以改善非線性失真;並結合靜態電流注入技術。
    本研究之晶片皆採用 On-Wafer 方式進行量測,並與模擬結果比較分析。量測結果顯示,低雜訊放大器於 5.5 GHz 具有 14.61 dB 增益、3.58 dB 雜訊指數及 -12.48 dBm 之 IIP3,功率消耗為 5.94 mW;混頻器於 LO 功率 0 dBm 時具有 9.21 dB 轉換增益、8.95 dB 雜訊指數、-3.83 dBm 之 IIP3 及 -12.69 dBm 之 P1dB,功率消耗約 10.26 mW。

    This thesis presents the design of a 5.5-GHz RF receiver front-end for IEEE 802.11a/ac WLAN applications, including a 5.5-GHz current-reuse low-noise amplifier and a 5.5-GHz active down-conversion Gilbert mixer, both implemented using the TSMC 0.18-μm CMOS process.
    The proposed low-noise amplifier employs a current-reuse architecture combined with a common-source topology and inductive source degeneration to achieve low power consumption while maintaining good input matching, high power gain, and low noise performance. The proposed mixer adopts a double-balanced Gilbert-cell architecture. To improve the circuit performance and design efficiency, the GM/ID design methodology together with load-line analysis is utilized to optimize the transistor dimensions and bias conditions. Furthermore, a Multiple-Gated Transistor (MGTR) linearization technique is incorporated into the transconductance stage to improve linearity, while a static current bleeding technique is employed.
    The fabricated chips were characterized using on-wafer measurements, and the measured results were compared with the post-layout simulations. The measured results of the LNA demonstrate a power gain of 14.61 dB, a noise figure of 3.58 dB, an input third-order intercept point of −12.48 dBm, and a power consumption of 5.94 mW at 5.5 GHz. For the proposed mixer, a maximum conversion gain of 9.21 dB is achieved with an LO input power of 0 dBm, together with a noise figure of 8.95 dB, an IIP3 of −3.83 dBm, a 1-dB compression point (P1dB) of −12.69 dBm, and a power consumption of 10.26 mW.

    第一章 緒論 1 1.1 研究背景與動機 1 1.2 文獻回顧 2 1.3 論文章節架構簡述 5 第二章 5.5GHz電流再利用低雜訊放大器電路設計 6 2.1 低雜訊放大器簡介 6 2.2 低雜訊放大器之重要參數 7 2.2.1 散射參數/ S 參數 (Scattering Parameter/ S-Parameter) 7 2.2.2 增益(Gain) 12 2.2.3 雜訊(Noise) 14 2.2.4 線性度(Linearity) 18 2.2.5 穩定度(Stability) 21 2.3 低雜訊放大器之基本架構 24 2.3.1 共閘極架構 (Common Gate) 24 2.3.2 電感性源極退化架構 (Inductive Source Degeneration) 25 2.3.3 電阻回授共源極架構 (Resistive Feedback Common Source) 26 2.4 電流再利用低雜訊放大器架構以及實現 27 2.4.1 研究背景與動機 27 2.4.2 電路設計流程 27 2.4.3 規格探討 29 2.4.4 架構選擇與簡介 31 2.4.5 電路設計說明與考量 36 2.5 模擬結果與探討 39 第三章 5.5 GHz 降頻式吉伯特混頻器電路設計 45 3.1 混頻器簡介 45 3.2 混頻器之重要參數 46 3.2.1 轉換增益(Conversion Gain) 46 3.2.2隔離度(Isolation) 46 3.2.3 線性度(Linearity) 47 3.2.4 雜訊(Noise) 48 3.3 混頻器之基本架構 49 3.3.1 平方律混頻器 49 3.3.2 被動式混頻器 50 3.3.3 主動式單平衡混頻器 51 3.3.4 主動式雙平衡混頻器 52 3.4 吉伯特混頻器架構以及實現 53 3.4.1 研究動機與背景 53 3.4.2 電路設計流程 54 3.4.3 規格探討 55 3.4.4 架構選擇與簡介 57 3.4.5 電路設計說明與考量 61 3.5 模擬結果與探討 69 第四章 量測結果與討論 77 4.1 電流再利用低雜訊放大器量測 77 4.1.1 量測環境設置 77 4.1.2量測結果與討論 79 4.2 吉伯特降頻式混頻器量測 85 4.2.1 量測環境與設置 85 4.2.2 吉伯特混頻器量測結果與討論 87 第五章 結論與未來展望 94 5.1 結論 94 5.2 未來展望 95 參考文獻 96

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