本論文提出一個應用於多通道神經紀錄系統的逐漸趨近與壓控震盪器混合式類比數位轉換器。配合實驗室的計畫預計做八通道前端類比感測電路來偵測神經訊號，本論文所提出的類比數位轉換器的規格為操作在160kS/s的取樣頻率且解析度需為10位元，混合式(Hybrid)架構結合了SAR ADC與VCO-based ADC，前者與後者分別為粗略與精細量化器，兩者比例為7:3，在VCO-based ADC的設計上，採用前饋交叉耦合、數餘數、Johnson counter等技術以降低其功率消耗，與傳統架構比較後，使用這些技術可以使VCO-based ADC的功耗的節省66.83%。另外，在震盪頻率的範圍上留有邊界，預防因雜訊與不匹配所造成的輸入殘值電壓偏移影響輸出結果，提升電路的可靠度。相比於使用單純10位元的SAR ADC，使用混合式架構可以讓電容陣列的大小減少8倍，等效於每通道的前端放大器功率消耗降低8倍，所以使用所提出之Hybrid ADC可以大大降低系統的功率消耗。
本論文使用了TSMC 0.18μm 1P6M的製程來實現晶片，量測結果如下 : SNDR為56.55 dB，FoM為0.1753 pJ/conv.，DNL與INL分別-0.577 / +0.594 LSB與-0.951 / +0.956 LSB，功率消耗則為15.238 μW。

This paper presents a hybrid analog-to-digital converter (ADC) combining successive approximation registers (SAR) with a voltage-controlled ring oscillator (VCO) for multi-channel neural recording. The proposed coarse-fine architecture can reduce the input capacitor load of the multi-channel analog front-end (AFE), which is beneficial for low-power design in a system overview. In the design of the VCO-based ADC, techniques such as feedforward cross-coupling, count remainder, and Johnson counter are used to reduce power consumption. Comparing with the traditional architecture, the utilization of these techniques can result in a power saving of 66.83% for the VCO-based ADC. In addition, the oscillation frequency range is set with a margin to avoid the impact of input residue voltage drift caused by noise and mismatch on the output results, enhancing the reliability of the circuit. Measurement results show that the proposed hybrid VCO-SAR ADC operating at 160-kS/s can achieve a signal-to-noise and distortion ratio (SNDR) of 56.55 dB while consuming 15.24 μW under 1.4/0.8 V supply, where the capacitor array is much less than a pure 10-bit SAR ADC to further ease the requirement of driving ability to the multi-channel AFEs.

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