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研究生: 楊大右
Yang, Ta-Yu
論文名稱: 應用CMOS製程研製之94 GHz混頻器與2.4 GHz壓控振盪器之探究設計
Research on 94 GHz Mixer and 2.4 GHz Voltage-Controlled Oscillator Designs in CMOS Processes
指導教授: 黃尊禧
Huang, Tzuen-Hsi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2024
畢業學年度: 113
語文別: 中文
論文頁數: 105
中文關鍵詞: 混頻器壓控振盪器40 nm180 nm
外文關鍵詞: Mixer, VCO, 40 nm, 180 nm
相關次數: 點閱:63下載:34
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  • 本論文之研究可分為二大主要部份:第一部份為使用TSMC 40 nm製程設計之混頻器,其頻率為94 GHz,該混頻器架構採用雙平衡式吉伯爾特混頻器(Double Balance Gibert Cell Mixer)進行設計,在設計上為了減輕負載端上電阻的壓降 (IR drop) 影響線性度,因此使用了電流注入 (Current bleeding) 技術提升線性度,並在輸出端加上共源極緩衝器 (Common source buffer) 提升整體轉換增益及共汲極緩衝器 (Common drain buffer)改善輸出阻抗。設計之效能主要以較高轉換增益(Conversion Gain)為主,因此在線性度(Linearity)效能上必須取得取捨,其模擬結果顯示:整體轉換增益約為7 dB,雜訊指數約為16.5 dB,線性度(IIP3)約為 1.85 dBm,功耗約為22.7 mW,晶片面積約為0.85 mm²。量測結果顯示: RF Return loss在頻率為94 GHz時約為 -4.2 dB,LO Return loss在頻率為94 GHz時約為 -4.3 dB,RF-LO Isolation約為 -39 dB,Conversion Gain在LO Power為1 dBm時,頻率為94 GHz下約為 -12.2 dB,IP1dB約為0 dBm。
    第二部份為使用TSMC 180 nm製程設計之壓控振盪器,其頻率為2.4 GHz,該振盪器架構採用考畢茲壓控振盪器(Colpitts)架構進行設計,設計主要以低功耗與相位雜訊為要點,共計有兩版電路。考畢茲振盪器相較於其他振盪器,具有相位雜訊(Phase Noise)較佳的優勢,但是起振條件較為嚴峻,可能導致功耗較大,為了解決此問題本次設計結合了電流再使用(Current reuse)的架構,藉由PMOS與NMOS共用一個VDD來達到電流降低之功用,以降低功耗。第一版電路量測結果顯示:晶片面積為0.785 mm²,其功耗為1.125 mW,頻率可調範圍為2.94 GHz ~ 2.33 GHz,頻率可調範圍為23.14%。相位雜訊在偏移1 MHz下為 -116.95 dBc/Hz。在第二版壓控振盪器之設計上沿用第一版架構,並進行些微調整設計。主要增加轉導提升(gm-boosting)之架構,該架構可以改善考畢茲振盪器天生起振條件較為困難的缺點,以利振盪器之功耗得以再減少。在效能上與第一版差異主要為在相位雜訊差不多情況下,降低了功耗的消耗,達到更低的功耗使用。其量測結果顯示:晶片面積為0.797 mm²,其功耗為0.993 mW,頻率可調範圍為2.83 GHz ~ 2.4 GHz,頻率可調範圍約為16.44%。相位雜訊在偏移1 MHz下為 -115.8 dBc/Hz。

    The research in this thesis can be divided into two main parts. The first part involves the design of a mixer using TSMC 40 nm technology, with a frequency of 94 GHz. This mixer employs a double-balanced Gilbert cell architecture. To mitigate the impact of the IR drop on the load resistance and enhance linearity, current bleeding technology is used. A common source buffer is added at the output to improve the overall conversion gain, and a common drain buffer is used to improve output impedance. The design primarily focuses on achieving higher conversion gain, which requires a trade-off with linearity. The simulation results show an overall conversion gain of approximately 7 dB, a noise figure of about 16.5 dB, linearity (IIP3) of around 1.85 dBm, power consumption of about 22.7 mW, and a chip area of approximately 0.85 mm². The measurement results show: RF Return loss is approximately -4.2 dB at 94 GHz, LO Return loss is around -4.3 dB at 94 GHz, RF-LO isolation is about -39 dB, the conversion gain is approximately -12.2 dB at 94 GHz when LO power is 1 dBm, and the IP1dB is around 0 dBm.
    The second part involves the design of a voltage-controlled oscillator (VCO) using TSMC 180 nm technology, with a frequency of 2.4 GHz. This VCO employs a Colpitts oscillator architecture, focusing on low power consumption and phase noise. Compared to other oscillators, the Colpitts oscillator offers better phase noise performance but has more stringent startup conditions, potentially leading to higher power consumption. To address this, the design incorporates a current reuse architecture, allowing PMOS and NMOS to share a single VDD to reduce current and lower power consumption. The first version measurement results indicate a chip area of 0.785 mm², power consumption of 1.125 mW, a frequency tuning range from 2.94 GHz to 2.33 GHz, and a frequency tuning range of 23.14%. The phase noise is -116.95 dBc/Hz at a 1 MHz offset. In the second version of the VCO, the design of the first version is retained with minor adjustments. The main enhancement is the addition of a transconductance boosting (g_m-boosting) architecture, which addresses the Colpitts oscillator's inherent difficulty in startup conditions, further reducing power consumption. Compared to the first version, the second version achieves similar phase noise performance with lower power consumption. The measurement results show a chip area of 0.797 mm², power consumption of 0.993 mW, a frequency tuning range from 2.83 GHz to 2.4 GHz, and a frequency tuning range of approximately 16.44%. The phase noise is -115.8 dBc/Hz at a 1 MHz offset.

    摘 要 I ABSTRACT III 誌 謝 XIV 目 錄 XV 表 目 錄 XVII 圖 目 錄 XVIII 第一章 緒論 1 1.1 研究背景與動機 1 1.2 文獻回顧 3 1.3 論文架構 4 第二章 94 GHz混頻器之設計 5 2.1 研究動機 5 2.2 混頻器簡介 6 2.2.1 混頻器之重要參數 7 2.2.2 混頻器架構介紹 14 2.3 混頻器電路設計 19 2.3.1 混頻器電路分析 19 2.3.2 設計流程 21 2.3.3 模擬結果 23 第三章 2.4 GHz壓控振盪器之設計 27 3.1 研究動機 27 3.2 壓控振盪器簡介 28 3.2.1 壓控振盪器架構介紹 29 3.2.2 壓控振盪器之重要參數 36 3.3 考畢茲壓控振盪器 41 3.3.1 架構選擇 41 3.3.2 電流再使用考畢茲壓控振盪器 45 3.3.3 模擬結果 49 3.4 轉導提升電流再使用考畢茲振盪器 55 3.4.1 振盪器電路設計 55 3.4.2 模擬結果 58 第四章 量測結果 63 4.1 混頻器量測 63 4.1.1 量測環境設置 63 4.1.2 量測結果與討論 66 4.2 壓控振盪器量測 70 4.2.1 量測環境設置 70 4.2.2 量測結果與討論 71 4.2.3 第二版量測結果與討論 74 第五章 結論 78 參考文獻 79

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