本論文提出一使用再生式除五除頻器實現之60-/24-GHz雙模共存的訊號源架構，並針對其前端電路進行設計與實現；電路部分分為兩大部分，包含V-band壓控振盪器和再生式除五除頻器；而再生式除五除頻器又包含一雙端輸出混頻器及一雙頻之除頻器兩個區塊，在論文中振盪器及除頻器兩個主要區塊皆使用TSMC 90-nm GUTM CMOS製程進行下線。
所設計之應用於V-band之壓控振盪器，使用錐狀傳輸線電感，並以浮接金屬層於電感底端和矽基板之間製造屏蔽，藉此降低由基板造成的損耗，設計上利用此電感之高Q值特性，能有效提升整體振盪器之Q值，使得振盪器在毫米波頻段能更容易單純直接使用可變電容，而不會受限於可變電容隨著頻率上升造成Q值下降的負面影響。在量測結果上，振盪器的頻率可調範圍有5.525 GHz，大約9.2%的變化比率；相位雜訊方面，在頻率偏移1 MHz處為-90.04 dBc/Hz，而整體核心電路在0.9 V的電源電壓下，功耗為13.53 mW。
再生式除五除頻器整體電路結合了一主動式混頻器和一串疊式除四除頻器，混頻器採用雙端輸出之Gilbert-cell架構，當輸入一5倍頻之訊號時，其會與回授回來之1倍頻進行混頻產生6倍頻及4倍頻，再濾除掉6倍頻後，4倍頻訊號會注入下一級串疊式除四除頻器，最後產生所需之訊號；而串疊式除四除頻器之部分由一注入式鎖定除二除頻器串疊(Cascode)一電流邏輯式除二除頻器組合而成，此架構能由下方注入式鎖定器直接輸出2倍頻，同時訊號能以電流形式注入上端電流邏輯式除頻器產生1倍頻，使得整體之再生式除頻器最後能夠同時輸出除數為5及2.5之訊號，其在電源電壓為1.6 V下總共消耗56.1 mW。

This thesis proposes an architecture of 60-/24-GHz dual-mode co-existence signal source circuit using a regernerative divide-by-5(DIV-5) divider, and the front end of the signal source including the V-band VCO and the DIV-5 divdier is designed and implemented. Furthermore, the regernerative divider includes a differential mixer and a dual-band frequency divider. Both of the two main blocks, the VCO and the divider in this thesis are fabricated by TSMC 90-nm GUTM CMOS process.
A tapered transmission line inductor is applied in the design of the V-band VCO. The floating metal strips are placed under the inductor in order to reduce the substrate loss. By using this high-Q factor inductor, it is efficient to improve the Q factor of the oscillator. After that, it’s easier to use varator directly in the design of the oscillator without any further technique since the VCO will not be limited by the side effect that the Q factor of the varator declines as the frequency rises. The frequency tuning range is 5.525 GHz (9.2%) observed from the measurment results. In addition, the phase noise of the VCO is -90.04 dBc/Hz at 1 MHz offset. The VCO core consumes 13.53 mW at 0.9 V supply voltage.
The regenerative divider consists of an active mixer and a cascode divide-by-4(DIV-4) divider. The mixer is composed of Gilbert-type cells. When the input signal is 5f0, the 5f0 will be mixed with the signal f0 from the feedback loop, then signal 4f0 and 6f0 are generated at the output of the mixer. After filtering out the 6f0, the signal 4f0 is injected into the DIV-4 divider stage to generate the wanted signal f0. And the DIV-4 divider is a cascode structure which composed of an injection-locked divide-by-2 divider (DIV-2 ILFD) and a current-mode logic (CML) divide-by-2 divider. In this structure, the divider can generate 2f0 at the output of the ILFD. Moreover, the signal will be injected into the cascode CML in the form of current to generate the signal f0. In this way, the regernerative divider has two division ratios 2.5 and 5 at the output of the ILFD and CML, respectively. The power consumtion is 56.1 mW at 1.6 V supply voltage.

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