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研究生： 程育賢
Cheng, Yu-Hsien
論文名稱： 在單晶片系統測試平台上對包覆IEEE 1500之待測電路進行延遲錯誤測試
IEEE 1500 Based On-Chip Delay Fault Testing
指導教授： 李昆忠
Lee, Kuen-Jong
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 60
中文關鍵詞： 單晶片系統 、延遲錯誤測試
外文關鍵詞： on-chip, delay fault testing
相關次數： 點閱：76  下載：2 
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    • 隨著半導體的發展日趨進步，系統單晶片的產生結合了不同功能的核心電路，大大地降低產品成本。然而以系統單晶片為基礎之設計方法仍然面臨許多挑戰。為了有效測試系統單晶片，通常使用的是具備大量記憶體配置、高頻率、高精準度的測試機台。但是，相對地其所需要的測試成本很高。除此之外，由於系統單晶片內的電晶體做得越來越小也越來越多，所以時間的延遲已經成為系統單晶片的主要問題。因此，如何利用較低成本來測試時間延遲是個迫切需要解決的課題。
    在本篇論文當中，我們提出了一個可以使用在單晶片系統測試平台上進行延遲錯誤測試的新方法，以支援包覆IEEE 1500核心電路的外部以及內部的延遲測試。在這項提出的新的方法裡，我們設計了一個延遲錯誤測試的控制器，不僅產生了針對外部的延遲測試所需的控制信號，同時也產生了在內部延遲測試下採用加強型掃描測試(enhanced scan test, EST)和觸發後擷取(launch off capture, LOC)方法的控制信號。因此，在內部延遲測驗當中，設計者可以選擇使用高錯誤涵蓋率的EST 方法或是在可接受的錯誤涵蓋率下使用較小面積的LOC方法。我們也進一步提出了一個針對在系統單晶片上當不同核心電路是操作在不同時脈的延遲錯誤測試方法。根據本項實驗結果顯示，這項新測試方法的確帶給延遲測試有直接在晶片上進行測試以及低面積的貢獻。

    Since the development of semiconductor has been greatly advanced, SoC is invented to integrate different functional cores to reduce the total cost of products. However, the SoC-based design methodology is facing lots of challenges nowadays. In order to test SoC effectively, the high cost ATE with large memory, high frequency, and great accuracy is normally used. Besides, as more and more transistors are squeezed into SoC with smaller size, timing defects have become the major problems on SoC. Therefore, testing the timing defects of SoC with low cost is a very important issue which needs to be discussed.
    This thesis presents a new on-chip delay testing mechanism to support external and internal delay test for IEEE 1500 wrapped cores. In the proposed on-chip delay testing mechanism, we design a delay fault test controller (DFTC) to generate not only the required control signals for external delay test but also the control signals for both enhanced scan test (EST) and launch off capture (LOC) methodologies of internal delay test. Thus, in internal delay test, designers are able to use either EST for high delay faults coverage or LOC for acceptable delay faults coverage with low area overhead. We further enhance the mechanism to deal with delay faults on SoC system with multiple system clocks. The experimental results show the effectiveness of the proposed on-chip delay testing mechanism.

    CHAPTER 1 INTRODUCTION 1 1.1. MOTIVATION 1 1.2. OVERVIEW TO THIS WORK 2 1.3. ORGANIZATION OF THESIS 3 CHAPTER 2 BACKGROUND AND PREVIOUS WORK 5 2.1. IEEE 1500 STANDARD 5 2.2. IEEE 1149.1 TAP CONTROLLER 7 2.3. DELAY TESTING SCAN METHODOLOGIES 8 2.3.1. Enhanced Scan Test (EST) 9 2.3.2. Launch Off Capture (LOC) (Broad-side) 9 2.3.3. Launch Off Shift (LOS) (Skewed-load) 10 2.4. EMBEDDED PROCESSOR BASED SOC TEST PLATFORM 11 2.5. PREVIOUS WORK 13 2.5.1. External Delay Test 13 2.5.2. Internal Delay Test 16 CHAPTER 3 SINGLE CLOCK DOMAIN ON-CHIP DELAY TESTING 20 3.1. THE HARDWARE COMPONENTS OF THE SOC TEST PLATFORM 20 3.1.1. TAM Controller 21 3.1.2. Test Bus 23 3.1.3. Delay Test Supporting Wrapper 23 3.2. THE DELAY TEST SUPPORTING WRAPPER 23 3.2.1. TAP Controller (TAPC) 24 3.2.2. Wrapper Instruction Register (WIR) 25 3.2.3. Wrapper Boundary Register (WBR) and Scan Cell 25 3.2.4. Delay Fault Test Controller (DFTC) 27 3.3. THE DELAY TEST PROCEDURES 30 3.3.1. External Delay Test 31 3.3.2. Enhanced Scan Test (EST) 33 3.3.3. Launch Off Capture (LOC) 35 CHAPTER 4 MULTIPLE SYSTEM CLOCKS DELAY TESTING 37 4.1. THE ENHANCED DELAY TESTING MECHANISM 37 4.2. THE ENHANCED DELAY FAULT TEST CONTROLLER 39 4.2.1. Signal Controller 39 4.2.2. FSM 41 4.2.3. Clock Gating Unit 41 4.2.4. Clock Generator 42 4.3. THE DELAY TEST PROCEDURES 44 4.3.1. External Delay Test 44 4.3.2. Enhanced Scan Test (EST) 46 4.3.3. Launch Off Capture (LOC) 48 4.4. COMPARISON 49 CHAPTER 5 EXPERIMENTAL RESULTS 51 5.1. EXPERIMENTAL ENVIRONMENT 51 5.2. EXPERIMENTAL RESULTS OF THE DELAY TESTING MECHANISM 52 5.3. EXPERIMENTAL RESULTS OF THE ENHANCED DELAY TESTING MECHANISM 53 CHAPTER 6 CONCLUSIONS AND FUTURE WORK 56 6.1. CONCLUSIONS 56 6.2. FUTURE WORK 57 REFERENCES 58

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