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研究生： 楊皓義
Yang, Hao-I
論文名稱： 動態可重新架構化之超純量處理器設計
Run-Time Reconfigurable Superscalar Processor Design
指導教授： 周哲民
Jou, rnJer-Min
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 英文
論文頁數： 78
中文關鍵詞： 處理器 、超純量 、重新架構化
外文關鍵詞： Superscalar.Processor, Reconfigurable
相關次數： 點閱：42  下載：1 
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    • 　　今日，資訊科技產業發展快速，微處理器在此產業中的腳色也愈來愈吃重。如何增進微處理器的效能成為一個非常重要的問題。另一方面，遮罩價格越來越昂貴，如何有效重新應用既有的電晶體變成為晶片設計中的一個重要課題。因此，可新架構化之處理器或許便是其中的一個解答。在本論文中，我們設計一個動態可重新架構化之超存量處理器，此處理器可做軟硬體共同執行。我們利用一個4乘4粗顆粒之可重新架構化單元陣列取代傳統超純量處理器所使用的功能運算單元，藉此結合可重新架構化的硬體與傳統的超存量處理器。在正常執行(即執行軟體程式)時，此陣列的行為與一般傳統處理器的功能單元相似；而在執行可重新架構化之運算(即執行硬體運算)時，此陣列的行為與特定功能基體電路相似。藉著結合可重新架構化之硬體，我們所設計的處理器將較一般傳統處理器更具有彈性與效率。

    　Today, “Information Technology (IT)” develops very fast, and microprocessors play more and more important roles in IT industry. Improving the performance of them is very important. Otherwise, the cost of mask is more and more expansive. How to reuse macro transistors is becoming more important for the IC design. Thus, the reconfigurable processor may be a solution. We design a run-time reconfigurable superscalar processor which can do hardware and software co-execution. Our design integrates a reconfigurable hardware with a traditional superscalar processor by replacing the traditional function units to a 4 by 4 coarse-grained reconfigurable component array. The behavior of the reconfigurable component array will be like tradition function units in the normal execution (software) and like ASICs in the reconfigurable computing execution (hardware). By combining with reconfigurable hardware, this run-time reconfigurable superscalar processor will be more flexible and more efficient then a traditional superscalar processor.

    CHAPTER 1 INTRODUCTION 1 1.1 GENERAL-PURPLE PROCESSORS 2 1.2 APPLICATION-SPECIFIC INTEGRATED CIRCUITS 2 1.3 RECONFIGURABLE DEVICES 3 1.4 RECONFIGURABLE PROCESSORS 3 1.5 MOTIVATION 4 1.6 THESIS ORGANIZATION 5 CHAPTER 2 RECONFIGURABLE PRINCIPLE AND APPLICATIONS 6 2.1 RECONFIGURABILITY AND CONFIGURABILITY 7 2.2 GRANULARITY 8 2.2.1 Fined- Grained Reconfigurable System 8 2.2.2 Coarse- Grained Reconfigurable System 8 2.2.3 Coarse-Grained V.S. Fine-Grained 9 2.3 CONFIGURATION PROCESS 10 2.4 RECONFIGURABLE PROCESSING COMPONENT COUPLING 11 2.5 SELF-RECONFIGURABLE COMPUTING 13 CHAPTER 3 INSTRUCTION SET 15 3.1 NORMAL INSTRUCTION SET 15 3.1.1 Normal Instructions 16 3.1.1 Reconfiguring Instructions 20 3.2 HARDWARE INSTRUCTION SET 21 3.3 THE ARCHITECTURE REGISTER FILE AND STATE REGISTERS 22 CHAPTER 4 RUN-TIME RECONFIGURABLE SUPERSCALAR PROCESSOR ARCHITECTURE 24 4.1 ARCHITECTURE OF THE PROPOSED RUN-TIME SUPERSCALAR PROCESSOR ARCHITECTURE 25 4.2 THE TRADITIONAL SUPERSCALAR PROCESSOR 26 4.2.1 Fetch 27 4.2.2 Decode 28 4.2.3 Rename 33 4.2.4 Issue 41 4.2.5 Readinging Operand 45 4.2.6 Execution 46 4.2.7 Retired and True Mapping Table 48 4.3 THE RECONFIGURABLE HARDWARE 50 4.3.1 The Reconfigurable Component 52 4.3.2 The RC Array 53 4.3.3 The Reconfigurable DMA 56 4.3.4 The Reconfigurable Controller and the Context Memory 57 4.3.5 Run-time Software and Hardware Co-execution 58 4.3.6 Mapping Function Units for the Normal Computation onto the RC Array 59 CHAPTER 5 ALGORITHM MAPPING AND PERFORMANCE ANALYSIS 61 5.1 2D CONVOLUTION 61 5.1.1 Mapping 2-D Convolution onto the RC Array 63 5.1.2 Mapping 2-D Convolution onto the RC Array with 8-bit Data Length 63 5.1.3 Mapping 2-D Convolution onto the RC Array with 16-bit Data Length 64 5.1.4 Analysis 66 5.2 DCT 69 5.3 FIR 72 CHAPTER 6 CONCLUSION 75 REFERENCE 77

    [1] Jer-Min Jou et al. “Adaptive Network-on-a-Chip Architecture System Design”, the 46th IEEE International Midwest Symposium on Circuits and Systems, 2003.
    [2] Jer-Min Jou. "Reconfigurable SoC Architectures," Proceedings of the VLSI Design/CAD Symposium, 2003.
    [3] Guangming Lu, “Modeling, Implementation and Scalability of the MorphoSys Dynamically Reconfigurable Computing Architecture”, Doctor of Philosophy in Electrical and Computer Engineering University of California, Irvine, 2000
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    [5] Hartenstein, R.: A decade of reconfigurable computing: a visionary retrospective. In: DATE,pp. 642 –649, 2001.
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    [7] E. A. Mirsky, “Coarse-Grain Reconfigurable Computing”, MIT, June, 1996
    [8] Shih-Lun Chen, Jer-Min Jou, Reconfigurable Processor Core Design for Network-on-a-Chip, EE NCKU, July 2004
    [9] Roman Lysecky, Frank Vahid, “A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning”, Design, Automation and Test in Europe Conference and Exhibition Volume I (DATE'04), February 2004
    [10] Shih-Lun Chen, Jer-Min Jou, Chien-Ming Sun, Yuan-Chin Wu, Haoi Yang, Hong-Yi Su,"Reconfigurable Processor Core Design for Network-on-a-Chip," ICS 2004, 2004
    [11] Adronis Niyonkuru, Hans Christoph Zeidler, Designing a Runtime Reconfigurable Process for General Purpose Application, Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International 26-30 April 2004 Page(s):143
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    [13] ARM Architecture Reference Manu, ARM, June 2000
    [14] ARM 7TDMI, ARM, August 1999.

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