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研究生: 楊竣崴
Yang, Jun-Wei
論文名稱: 平行化JPEG編碼器於單晶片多處理器平台上之研究與設計
A Parallel JPEG Encoder Design on a MPSoC Platform
指導教授: 周哲民
Jou, Jer-Min
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 83
中文關鍵詞: 多處理器平台影像壓縮
外文關鍵詞: jpeg encoder, MPSoC
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  • 近年來多媒體應用有越來越複雜的趨勢,如3D遊戲及影像壓縮…等,若將之實現在嵌入式系統卻一件不簡單的事,因為必須考慮到應用程式的複雜度、高效能的晶片設計及產品及時上市的種種問題,而這些問題在單處理器上似乎越來越難解決,因此高效能的內建網路通訊的晶片(Network-on-Chip)的研究與發展便油然而生,此NoC平台允許設計者能在系統晶片(System-on-Chip)上快速整合眾多的矽智財(SIP),而我們亦稱此系統平台為多處理器系統單晶片(Multi-Processor SoC),而此MPSoC平台能在同一時間即時提供大量的處理量。
    在此論文中,一個分散式JPEG編碼器將應用在NoC平台上的多處理器系統,不同以往JPEG編碼器應用在單處理器上,我們將JPEG編碼器切割給數個區塊,再將各個區塊分別分派給NOC平台上的不同處理器去做平行處理,而且處理效能會比單處理器來得更好,尤其是處理越大的圖片,效果越顯著。而在此次的測驗中我們利用多處理系統上的4個處理器來做JPEG編碼的動作,最多處理效能可提升180%。

    Recently, there is a trend towards complex multimedia applications, such as 3D games and video compression, implemented by embedded devices. The implementation of these applications on small and fixed devices is a very difficult task, due to the divergence and the complexity of embedded applications, the higher chip design cost, and the shorter time-to-market. To meet these requirements, single core (or single processor) systems are not capable of providing the required computational power for such complex applications. Thus a high performance platform-based design approach called Network-on-Chip (NoC) should be applied. The platform-based NoC paradigm allows the designers to fast integrate (and reuse) tens of Silicon Intellectual Property (SIP) cores in a single System-on-Chip (SoC), and a NoC-based Multi- Processor SoC (MPSoC) can provide the computational concurrency required to handle concurrent events in real- time.
    In the thesis, a distributed JPEG encoder on a NoC-based MPSoC platform is presented. Unlike the traditional JPEG encoder designed with a single core, first this new JPEG encoder is partitioned into some parallel threads, which are then mapped to the processor cores of the scalable NoC-based MPSoC platform respectively. Therefore, it can be executed concurrently and distributedly, and the performance is better than that of the single-core design, especially as processing larger pictures. The results show that the encoding performance with 4 processor cores indeed increases up to 180 %.

    目錄 i 表目錄 iv 圖目錄 v 第一章 緒論 1 1.1 研究動機 1 1.2 研究目的 1 1.3 論文架構 1 第二章 研究背景 2 2.1 JPEG 編碼設計 2 2.1.1 JPEG 編碼器PSNR(Peak Signal to Noise Ratio)比較 7 2.2 MPSoC系統平台 9 2.2.1 C++發展環境 11 2.2.2硬體模擬器 11 2.2.3 FPGA 13 第三章 MPSoC系統架構 14 3.1 MPSoC之處理器架構 14 3.1.1 NETWORK INTERFACE 23 3.1.2 MEMDEV 26 3.2 MPSoC之路由器架構 27 3.2.1 router 28 3.2.2 Sub router 30 3.3 硬體合成 32 第四章 JPEG平行化軟體設計 35 4.1 平行化應用程式開發背景 35 4.1.1 平行化軟體設計流程 35 4.1.2 平行化軟體之處理器映射方法 36 4.2平行化軟體設計之傳輸協定 39 4.2.1 C library 39 4.2.2 傳輸協定 42 4.3 JPEG 編碼器分析與切割 49 4.3.1 JPEG編碼器執行流程分析 49 4.3.2程式切割方式平行化 55 4.3.3資料切割方式平行化 59 4.3.4 Motion JPEG編碼平行化 63 第五章 平行化JPEG編碼器實驗 65 5.1 程式切割平行化驗證 65 5.2資料切割平行化驗證 73 5.3 Motion JPEG平行化驗證 78 第六章 結論與未來發展 81 參考文獻 83

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