| 研究生: |
許績耀 Hsu, Chi-Yao |
|---|---|
| 論文名稱: |
使用可重組化FPGA於OFDM中之2048點即時FFT設計 Design of 2048-point Real-Time FFT of OFDM by Using Reconfigurable FPGA |
| 指導教授: |
賴源泰
Lai, Yen-Tai |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2004 |
| 畢業學年度: | 92 |
| 語文別: | 英文 |
| 論文頁數: | 53 |
| 中文關鍵詞: | 快速傅立葉轉換 、可重組化 |
| 外文關鍵詞: | reconfigurable, FFT |
| 相關次數: | 點閱:64 下載:2 |
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可重組化架構的出現開啟了一個新的實現應用的選擇,但也產生了一些新的在設計上的挑戰。在動態可重組化架構中,針對任意應用來說,選擇一個有效率的架構及選擇一個適合的可重組化方案是項複雜的工作。
因可重組化架構多使用可重組化現場可程式邏輯閘陣列來實現應用,故本研究嚐試使用現場可程式邏輯閘陣列來實現快速傅立葉轉換。在處理一個框架的時間中,有數個區塊依序被運算於相同的硬體上。我們提出一個分析用方程式來計算實現快速傅立葉轉換所需的最小硬體資源,同時可利用它來選擇適合的可重組化方案。
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectures, the choice of an efficient architecture and reconfiguration scheme for an application is a complex task.
Since reconfigurable architectures use reconfigurable FPGA to implement applications, the research tries to use reconfigurable FPGA to implement FFT. During a frame duration, several blocks are computed sequentially on the same hardware. We provide analysis equations to compute needed minimal resources and to choose adaptive
reconfiguration schemes for FFT.
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