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研究生：	蔡佳原 Tsai, Jia-Yuan
論文名稱：	單相新型多階層換流器研製 Study and Implementation of a Single-Phase Novel Multilevel Inverter
指導教授：	陳建富 Chen, Jiann-Fuh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	54
中文關鍵詞：	多階層換流器、全橋換流器、數位訊號處理器
外文關鍵詞：	multilevel inverter, H-bridge inverter, DSP (Digital Signal Processor)
相關次數：	點閱：72 下載：2
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本論文主旨在於研製一新型多階層換流器。主要架構多使用兩個功率開關，使提出之換流器可以六個功率開關即輸出五個階層的電壓。由於功率元件減少，因此可達成高功率密度及縮小電路體積，並可同時達成低輸出諧波及縮小濾波器體積，如此可降低電路成本並簡化多階層換流器設計。文中將會說明電路之動作原理及控制流程。最後將研製一輸出功率為1.2 kW之實驗室雛形電路來驗證電路效能，控制部份將由數位訊號處理器(Digital Signal Processor, DSP)來實現，並提出延伸電路。

In this study, a novel multilevel inverter topology is proposed. By using two additional power components, the proposed inverter which is composed of six power switches can achieve five levels output. With less components, higher power density and small volume of circuit can be realized. Thus, low harmonic distortion is achieved and small size output filter is used. In this way, the total cost of the circuit can be reduced and the design procedure of overall system can be simplified. The detail of mode analysis and the control method are introduced. Finally, a laboratory prototype circuit is realized to verify the performance. The control scheme is presented by DSP (Digital Signal Processor) and the extended topology is proposed.

CONTENTS
Chinese Abstract……………………………………………………………I
Abstract……………………………………………………………………II
Acknowledgement…………………………………………………………III
CONTENTS………………………………………………………………IV
List of Figures………………………………………………………………VI
List of Tables……………………………………………………………VIII
Chapter 1. Introduction……………………………………………………1
    1.1 Backgrounds and Motivations………………………………………1
    1.2 Organization of Thesis………………………………………………2
Chapter 2. Existing Multilevel Topologies…………………………………3
    2.1 Diode-Clamped Inverter……………………………………………3
2.2 Capacitor-Clamped Inverter…………………………………………7
2.3 Cascaded H-Bridge Inverter………………………………………13
2.4 Simplified Multilevel Inverter……………………………………16
2.5 Multilevel Inverter Using Switched Series/Parallel DC Voltage 
Sources……………………………………………………………17
2.6 Switched-Capacitor Multilevel Inverter Using Series/Parallel DC 
Conversion………………………………………………………… 20
2.7 Conclusions of Existing Multilevel Topologies……………………22
Chapter 3. Study and Operating Principle of Novel Multilevel    
          Inverter………………………………………………………25
3.1 Proposed Circuit Topology…………………………………………25
3.2 Mode Analysis of Proposed Topology……………………………26
3.3 Simplified Control Method of Proposed Topology………………31
3.4 Simulation Results of Proposed Circuit……………………………37
3.5 Extended Circuit of Proposed Topology…………………………40
Chapter 4. Experimental Results of Novel Multilevel Inverter…………42
4.1 Specification of Circuit and Implementation of Control Method …42
4.2 Experimental Results of the Proposed Topology…………………46
4.3 Discussion of Simulation and Experimental Results…………… 48
Chapter 5. Conclusions and Future Study………………………………49
5.1 Conclusions………………………………………………………49
5.2 Future Study………………………………………………………50
References…………………………………………………………………51



List of Figures
Fig. 2.1 Three-Levels Diode-Clamped Inverter………………………………3
Fig. 2.2 Five-Levels Diode-Clamped Inverter ……………………………… 4
Fig. 2.3 Five-Levels Diode-Clamped Inverter with Same Diode 
      Specification…………………………………………………………6
Fig. 2.4 Three-Levels Diode-Clamped Inverter………………………………8
Fig. 2.5 Five-Levels Capacitor-Clamped Inverter ……………………………8
Fig. 2.6 Five-Levels Capacitor-Clamped Inverter with Same Voltage on 
       each capacitor………………………………………………………11
Fig. 2.7 Three-Levels H-Bridge Inverter……………………………………13
Fig. 2.8 Five-Levels Cascaded H-Bridge Inverter …………………………15
Fig. 2.9 Simplified Multilevel Inverter ……………………………………17
Fig. 2.10 Switched Series/Parallel DC Voltage Sources Multilevel Inverter.18
Fig. 2.11 Extended Switched Series/Parallel DC sources Circuit…………19
Fig. 2.12 Switched Series/Parallel Capacitors Multilevel Inverter…………20
Fig. 2.13 Extended Switched Series/Parallel Capacitors Circuit …………22
Fig. 3.1 Novel multilevel inverter topology………………………………26
Fig. 3.2 Mode Analysis ……………………………………………………28
    (a) Mode I: Vab equals to Vdc……………………………………28
    (b) Mode II: Vab equals to Vdc/2…………………………………29
    (c) Mode III: Vab equals to 0………………………………………29
    (d) Mode III: Vab equals to 0………………………………………30
    (e) Mode IV: Vab equals to -Vdc/2…………………………………31
    (f) Mode V: Vab equals to -Vdc……………………………………32
Fig. 3.3 Simplified Multilevel SPWM modulation method…………………33
Fig. 3.4 Simplified Multilevel SPWM modulation method flowchart………37
Fig. 3.5 Simulation results of multilevel output Vab…………………………39
Fig. 3.6 Simulation results of filtered output Vo ……………………………39
Fig. 3.7 FFT simulation results of filtered output Vo ………………………40
Fig. 3.8 Extended circuit of proposed topology ……………………………41
Fig. 4.1 Utility grid voltage vs. PWM signals of S3&S4……………………44
Fig. 4.2 PWM signals of S3, S1&S6…………………………………………44
Fig. 4.3 PWM signals of S3, S5&S6…………………………………………45
Fig. 4.4 PWM signals of S4, S2&S5…………………………………………45
Fig. 4.5 Voltage waveform of Vab……………………………………………46
Fig. 4.6 Voltage waveform of Vo……………………………………………47
Fig. 4.7 Voltage waveform of Vab & Vo………………………………………47
Fig. 4.8 Fourier analysis of Vo………………………………………………48
Fig. 4.9 Energy conversion efficiency………………………………………49
List of Tables
Table I. Comparison between Diode-Clamped Inverter………………………6
Table II. Charge and Discharge Mode………………………………………12
Table III. Comparison between Capacitor-Clamped Inverter………………12
Table IV. Comparison between Cascaded H-Bridge Inverter………………15
Table V. Necessary parts of Simplified Multilevel Inverter…………………17
Table VI. Comparison of component numbers………………………………24
Table VII. Output voltage level related to the switches state……………… 27
Table VIII Simulation parameters of proposed circuit………………………38
Table IX. Specification of Key Components………………………………43
Table X. Specification of Circuit Parameters………………………………43 

                                    

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校內：2017-07-27公開
校外：2017-07-27公開

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