本論文主要分為兩個部分，第一部分是具互補式自切換偏壓機制(Complementary Self-Switching Bias Technique)之5.5 GHz 壓控振盪器設計，第二部分是使用快速相位誤差校正(FPEC)技術之3.5 GHz 切換式迴路濾波器(SLF)鎖相迴路設計。本論文中所設計之電路皆是使用TSMC 0.18 μm 1P6M製程實現，並以on-wafer方式完成量測。
在第一部分中透過自切換偏壓技術來降低尾電流源(tail current)電晶體的閃爍雜訊(flicker noise)達到低相位雜訊之功效。在 LC共振腔振盪器結構中，尾端電流源產生的閃爍雜訊是近端相位雜訊(close-in noise)的主要貢獻者。自切換偏壓技術的核心原理在於透過電容耦合將振盪信號回饋至尾端電流源的閘極，迫使電晶體在強反轉區(strong inversion region)與累積區(accumulation region)之間週期性切換。這種物理機制能有效移除電晶體內部陷阱的長期記憶效應，直接降低閃爍雜訊功率。
第二部分為使用快速相位誤差校正技術之切換式迴路濾波器鎖相迴路，是一種結合了快速相位誤差校正與切換式迴路濾波器的高性能鎖相迴路架構，快速相位誤差校正技術，這項技術透過模擬注入鎖定時脈倍增器(ILCM)中的比例區間(T_PROP)，以密集且瞬時的方式移除大部分相位誤差；隨後再藉由積分區間(T_INT)提供高穩定性與頻率追蹤能力，進一步提升整體系統效能。本電路之量測參考頻率為109.375MHz，除數為32，因此輸出頻率為3.5 GHz。在1 MHz偏移頻率下，相位雜訊為 -103.07 dBc/Hz，而1 kHz 至100 MHz範圍內的積分時脈抖動(integrated clock jitter)為 1.1 ps。鎖相迴路可在30 μs內完成頻率鎖定。包含輸出緩衝器在內之鎖相迴路總功耗為 21 mW。

This thesis is mainly divided into two parts. The first part presents the design of a 5.5 GHz voltage-controlled oscillator (VCO) with a complementary self-switching bias technique, while the second part presents the design of a 3.5 GHz switching loop filter phase-locked loop (SLF-PLL) using a Fast Phase Error Correction (FPEC) technique. All circuits in this thesis were implemented using the TSMC 0.18 μm 1P6M CMOS process and measured through on-wafer testing.
In the first part, a self-switching bias technique is adopted to reduce the flicker noise of the tail current source transistor, thereby improving phase noise performance. In LC-tank oscillators, the flicker noise generated by the tail current source is one of the major contributors to close-in phase noise. The core concept of the self-switching bias technique is to feed the oscillation signal back to the gate of the tail current source transistor through capacitive coupling, forcing the transistor to switch periodically between the strong inversion region and the accumulation region. This physical mechanism effectively removes the long-term memory effect of internal traps in the transistor and directly reduces flicker noise power.
The second part presents a switched loop filter PLL using the Fast Phase Error Correction (FPEC) technique, which combines FPEC and a switched loop filter (SLF) to achieve a high-performance PLL architecture. The FPEC technique removes most of the phase error rapidly and intensively during the proportional interval(T_PROP) of an Injection-Locked Clock Multiplier (ILCM). Subsequently, the integral interval(T_INT) provides high stability and frequency tracking capability, further enhancing overall system performance. The measured reference frequency is 109.375 MHz with a division ratio of 32, resulting in an output frequency of 3.5 GHz. At a 1 MHz offset frequency, the phase noise is -103.07 dBc/Hz, while the integrated RMS jitter from 1 kHz to 100 MHz is 1.1 ps. The PLL achieves frequency lock within 30 μs. The total power consumption of the PLL, including the output buffer, is 21 mW.

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