近年來消費者益愈重視產品的便利及娛樂性，智慧型人機介面因此扮演重要的腳色，並促進語音辨識系統相關研究及發展。為了滿足低成本需求之語者獨立語音辨識晶片設計，本研究提出了超低緩衝器架構(Ultra-Low Buffer Method)在有限的記憶體資源上實現語音特徵萃取參數運算，節省了96.48%自相關係數運算記憶體資源並提升256倍的自相關係數運算反應時間；另外，亦改良線性預測倒頻譜係數(Linear Prediction Cepstral Coefficients, LPCC)特徵萃取程序步驟並做電路最佳化，同步精簡電路面積、運算量及關鍵路徑(Critical Path)。最後，採取複雜度低準確率高的動態時間校準演算法(Dynamic Time Warping, DTW)作為辨識方法，有效實現低成本需求的晶片硬體設計。
我們利用晶片設計製作中心(Chip Implementation Center, CIC )與台灣積體電路公司(TSMC)所提供的0.9製程梯次(TN90MSG-102A)完成本晶片實作下線(Tape-Out)。晶片面積為1.16*1.16 mm2，以48支接腳封裝，閘總數(Gate Count)約為43609，消耗功率為1.006 mW，工作頻率為10MHz，取樣頻率為4kHz。

In this study, to achieve a low cost chip design for speaker-independent automatic speech recognition (ASR) system, a novel ultra-low buffer method is proposed to realize the feature extraction operation in limited memory resources. Total 96.48% memory requirement of autocorrelation computation can be reduced and the response time of the autocorrelation computation for one frame can be performed 256 times improvement. Besides, the improved linear prediction cepstral coefficients (LPCC) feature extraction procedure and its related optimized circuits reduce the dedicated hardware area, computational requirements, and the critical path. Finally, the low-complexity and high-accuracy dynamic time warping (DTW) classifier is adopted as the recognition part in this ASR system to efficiently implement the low cost chip design.
This study has been taped-out in TSMC’s 90nm process via Chip Implementation Center (CIC). The chip area is 1.16*1.16 mm2, 48-pin package, gate count is 43609, and the power dissipation is 1.006 mW. The operation frequency is 10 MHz, while the Sampling rate is 4 kHz.

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