在大多數的數位與混合訊號電路中會大量的使用時脈訊號(clock)來控制電路的觸發。在高頻操作下，時脈訊號的頻率、相位以及脈波寬度等特性之精確度在電路應用上十分重要。目前的鎖相迴路(PLL)及延遲鎖定迴路(DLL)在訊號頻率與相位的校正上，已經能夠有相當不錯的表現。至於在脈波寬度控制部份，針對在Duty Cycle為50%的議題上，也已經有良好的研究成果被提出；然而在控制Duty Cycle為非50%的研究上，必須採用多個電流源及開關控制電路來實現脈波寬度的調整，使得在晶片面積、功率消耗與設計複雜度上大為提升，同時造成成本的提高。而本論文針對周期性訊號提出一個簡單方法來調整其Duty Cycle。
在本論文中，我們首先針對近年來應用於脈波寬度控制迴路的電路設計進行分析探討，並分析各種方法的優點與所面臨的挑戰。其次，我們改良傳統的PWCL電路，提出一個僅需加入簡單的數位除頻器，即可達到控制脈波寬度的功能。實驗結果顯示，經由此電路的校正結果，可得到輸出的脈波Duty Cycle為50%、33%(67%)，且具有小面積及低功率消耗的優點。最後，我們分析此電路在不同的頻率及Duty Cycle下所能達到校正的功能，並提出改良方法，並發展此電路可應用於其它脈波Duty Cycle為25%、75%以及更多的Duty Cycle 選擇的可能性。
本論文所提出的利用數位除頻器實現簡易型時脈寬度控制迴路電路之設計的主要功能區塊皆以TSMC 0.35m CMOS 2P4M 製程進行模擬驗証，實驗結果顯示其可得到不錯的效能。

Most digital and mixed-signal circuits use a lot of clock signals to trigger a periodic notification at the requested time. The accuracies on frequencies, phases and pulse widths of clock signals are very important for high speed applications. For the issues of adjustment on frequency and phase of a signal, current phase locked loop (PLL) and delay locked loop (DLL) technologies have achieved good results in recent years. For the topics of pulse width control for a given signal, many good research results have been presented to deal with the specific case of balanced duty cycle (duty cycle is 50%). However, on the subject of unbalanced duty cycle (duty cycle is not 50%) adjustment, current design must employ many extra current sources and switches to accomplish duty cycle adjustment. Such a method raises the chip area, power consumption and design complexity, and consequently increases the cost. This thesis proposes an alternative method which can regulate duty cycle of a periodic signal.
In this thesis, we first survey recently published design of pulse width control loop circuits, and analyze the advantages and challenges of each method. Secondly, we modify the traditional PWCL circuit by using a simple frequency divider to achieve the goal of duty cycle regulation. The experimental results show that the duty cycle can be correctly adjusted to 50%, 33% (67%), and the proposed design has advantages of small chip area and low power consumption. Finally, we analyze this circuit performance and present an improvement method for different frequencies and duty cycles
All major function blocks proposed in this thesis are all verified and simulated with TSMC 0.35m 2P4M CMOS process. The experimental results show a good agreement with the analysis.

[1] M. Fenghao and C. Svensson, “Pulsewidth Control Loop in High-Speed CMOS Clock Buffers,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 134–141, Feb. 2000.
[2] J.-S. Wang, C.-F. Hu, and Y.-M. Wang, “An A11-Digital Pulse-Width Locked Loop,” M.S. Thesis, Department of Electrical Engineering National Chung Cheng University, Taiwan, 2002.
[3] S.H.-L. Tu, “Design and Implementation of Differential Pulsewidth Control Loop for GHz VLSI Systems,” Electronics Letters, 18th Aug. 2005, vol. 41, no. 17.
[4] H.-T. Ahn and D. J. Allstot, “A Low-Jitter 1.9-V CMOS PLL for Ultra-SPARC Microprocessor Applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 450–454, Mar. 2000.
[5] D. W. Boerstler, “A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340–612 MHz,” IEEE J. Solid-State Circuits, vol. 34, pp. 513–519, Apr. 1999.
[6] J. Lee and B. Kim, “A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control,” IEEE J. Solid-State Circuits, vol. 35, pp. 1137–1145, Aug. 2000.
[7] K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, and M. Yotsuyanagi, “A CMOS 50% Duty Cycle Repeater Using Complementary Phase Blending,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2000, pp. 48–49.
[8] Y. Moon, J. Choi, K. Lee, D. K. Jeong, and M. K. Kim, “An All-Analog Multiphase Delay-Locked Loop Using Replica Delay Line for Wide-Range Operation and Low-Jitter Performance,” IEEE J. Solid-State Circuits, vol. 35, pp. 377–384, Mar. 2000.
[9] T. Ogawa and K. Taniguchi, “A 50% Duty-Cycle Correction Circuit for PLL Output,” in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, 2002, pp. 21–24.
[10] Y. J. Jung, S.W. Lee, D. Shim, W. Kim, C. H. Kim, and S. I. Cho, “A Low Jitter Dual Loop DLL Using Multiple VCDL’s with a Duty Cycle Corrector,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2000, pp. 50–51.
[11] B. Razzavi, “Design of Analog CMOS Integrated Circuits,” New York: McGraw-Hill, 2001.
[12] D. Johns and K. Martin, “Analog Integrated Circuit Design,” New York: Wiley, 1997.
[13] Sung-Rung Han and Shen-Iuan Liu, “A Single-Path Pulsewidth Control Loop With a Built-In Delay-Locked Loop,” IEEE J. Solid-State Circuits, vol. 40, no. 5, May 2005, pp. 1130-1135.
[14] Christopher Lam and Behzad Razavi, “A 2.6GHz/5.2-GHz Frequency Synthesizer in 0.4μm CMOS Technology,” IEEE J. Solid-State Circuits, vol.35, May 2000, pp. 788 –7940.
[15] Wei Wang, I-Chyn Wey, Chia-Tsun Wu, and An-Yeu (Andy) Wu, “A Portable All-Digital Pulsewidth Control Loop for SOC Applications,” 2006 IEEE ISCAS 2006, pp. 3165-3168.
[16] Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu and Shen-Iuan Liu, “A 900-MHz 1-V CMOS Frequency Synthesizer,” IEEE J. Solid-State Circuits, vol.35, Aug. 2000, pp. 1211-1214.
[17] Wei-Ming Lin and Hong-Yi Huang, “A Low-Jitter Mutaual-Correlated Pulsewidth Control Loop Circuit,” IEEE J. Solid-State Circuits, vol.39, Issue 8, Sept. 2004, pp. 1366 – 1369.
[18] Hong-Yi Huang, Wei-Ming Chiu and Wei-Ming Lin, “Pulsewidth Control Loop Circuit Using Combined Charge Pumps and Miller Scheme,” in Proc. IEEE International Conference on Solid-State and Integrated Circuits Technology, Oct. 2004, pp.1539 – 1542.
[19] Po-Hui Yang and Jinn-Shyan Wang, “Low-Voltage Pulsewidth Control Loop for SOC Applications,” IEEE J. Solid-State Circuits, vol.37, Oct. 2002, pp.1348–1351.
[20] Jinn-Shyan Wang and Po-Hui Yang, “Low-Voltage CMOS Pulsewidth Control Loop Using Push-Pull Charge Pump,” Electronics Letters, vol.37, Mar. 2001, pp. 409–411.
[21] Sung-Rung Han, and Shen-Iuan Liu, “A 500-MHz–1.25-GHz Fast-Locking Pulsewidth Control Loop With Presettable Duty Cycle,” IEEE J. Solid-State Circuits, vol. 39, no. 3, Mar. 2004, pp. 463-468.
[22] Steve Hung-Lung Tu, “A Differential Pulsewidth Control Loop for High-Speed VLSI Systems,” IEEE Transactions On Circuits And Systems—II: Express Briefs, vol. 53, no. 5, May 2006, pp. 417-421.
[23] Kuo-Hsing Cheng, Chia-Wei Su, Chen-Lung Wu and Yu-Lung Lo, “A Phase-Locked Pulsewidth Control Loop with Programmable Duty Cycle,” 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC2004) I, Aug. 4-5, 2004, pp. 84-87.
[24] Hong-Yi Huang, Chia-Ming Liang and Wei-Ming Chiu, “1-99% Input Duty 50% Output Duty Cycle Corrector,” 2006 IEEE ISCAS 2006, pp. 4175-4178.