電子式影像感測元件目前由電荷耦合式與互補式金屬氧化半導體做為主要架構，近來則由於低耗能訴求與單晶片趨勢等市場因素影響，使互補式金氧半影像感測器逐漸在相關領域裡嶄露頭角，並有取代電荷耦合式影像感測器成為主流之勢；然而，電晶體特性造成的雜訊與限制使此種影像感測器無法提供接近人類眼睛的動態範圍，為使應用層面擴大，高動態範圍之影像感測器遂成為極力研究開發的議題。

有鑑於上述現象，本論文設定互補式金氧半影像感測器之動態範圍為研究方向，並且以低功率與低成本作為設計原則。首先，探討互補式金氧半影像感測器之動態範圍特性，接著針對現有提高動態範圍技術之缺點由類比電路設計的角度提出像素單元修正方案，包括雙光二極體的使用、電荷釋出技巧與自變型電容的配置共三種方法，再透過模擬決定設計晶片之參數。最終，在電路佈局完成後送交製作，並藉由晶片之量測驗證設計的可行性。量測的數據得到動態範圍提昇 7~17dB 之成果，且不增加任何多餘功率的消耗，並期許未來進一步改善整體電路之效能與實用性。

研究晶片經由財團法人國家實驗研究院晶片系統設計中心贊助，使用台灣積體電路公司 0.18μm 1P6M 3.3V 混合訊號互補式金屬氧化半導體製程完成，晶片之面積為 1.193×0.813 mm2。像素陣列採用 3-T 架構的主動式像素感測器，以及 N型井/P型基板構成接面的光二極體，包括有三種設計，並藉由增加不同參數之組合增加分析所需要的參考資料。

Electronic image-sensing device currently comprises CCD (charge-coupled device) and CMOS (complementary metal-oxide-semiconductor) technology, while the tendency towards low power consumption and system-on-chip (SOC) integration led by the market makes CMOS image sensor stand out conspicuously in related fields and obtain a major stance gradually, substituting for CCD image sensor; however, the noises and limitations influenced by characteristics of transistors result in the lack of dynamic range close to the one of human eyes be implemented in this kind of image sensor, and in order to broaden the scope of several applications, high dynamic range image sensor becomes a subject under research and development.

As a result of the above phenomenon, this thesis would like to take dynamic range of a CMOS image sensor as the research goal. At the beginning, the dynamic range characteristics of CMOS image sensor would be realized, followed by introducing pixel cell modification plans in an analog design perspective toward the shortcomings of dynamic range increment in present techniques through the usage of double photodiodes, a technique of releasing charges and an implementation of a self variable capacitor, totally three kinds of methods and the decision of proposed chip’s parameters is then determined by circuit simulation. The chip is produced after completion of circuits’ layout in the end and the verification is done by measurement of complete chip to check its practicability. An increment of 7 to 17dB in dynamic range is obtained through measurement and there is not any additional power consumption needed for its achievement, thus further efficiency and practicability for the whole circuits could be a future plan.

The proposed chip, with a die area of 1.193×0.813 mm2, is patronized by National Applied Research Laboratories National Chip Implementation Center (NARL NCIC), accomplished by using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm 1P6M 3.3V mixed-signal CMOS process. Pixel arrays adopt 3-T active pixel sensor (APS) and photodiode which composed of NW/Psub junction and include three types of design that used for gathering the reference data needed for analysis by increasing different parameter combination in the chip.

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