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研究生: 吳俊杰
Wu, Chun-Chieh
論文名稱: 應用於植入式醫療通訊頻段之非整數式鎖相迴路
A Fractional-N PLL for MICS Band Application
指導教授: 羅錦興
Luo, Ching-Hsing
共同指導教授: 黃弘一
Huang, Hong-Yi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 中文
論文頁數: 100
中文關鍵詞: 電壓控制振盪器非整數式鎖相迴路主動式電感自動校正機制
外文關鍵詞: Voltage control oscillator, Fractional-N PLL, Active inductor, Calibration
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  • 在現今的無線通訊系統上,頻率合成器擁有著相當重要的位置,並且隨著不同的應用頻段會有著不同的規格需求。在本論文中是針對一個應用於生醫植入式通訊系統(Medical Implantable Communication System, MICS)的頻段來做應用與設計,而此系統應用頻段為,402MHz~405MHz且channel space 為300KHz擁有十個頻段可供切換。
    而非整數式鎖相迴路則是實現頻率合成器的方式之ㄧ,在本論文中提出使用主動式電感與自動校正機制之非整數式鎖相迴路,此電路提供了一較寬的輸出頻率範圍避免因振盪器的漂移導致電路工作不正常以及較小的晶片面積需求。利用了主動式電感降低被動電感的面積需求以及迴路濾波器之電容皆使用MOS替代,可大幅度的降低對MIM電容面積的浪費與成本。在配合上自動校正機制,可盡量避免製程、溫度、電壓變異所造成的影響。非整數式鎖相迴路晶片的製作是利用台積電0.18-um 1P6M之製程所製作,其操作頻率為218-MHz到466-MHz,phase noise @ 1MHz 為-105.6dBc/Hz。整體晶片的面積為825 730 um2(中心電路:450 385 um2),操作頻率402-MHz時,其功率消耗約為5.13 mW(不含output buffer)。

    The frequency synthesizer circuit is an important part of wireless communication system. Due to different communication applications, the requirements of the frequency synthesizer specifications are also dissimilar. In this work, the frequency synthesizer circuit is designed for Medical Implantable Communication System (MICS) application. The operating range of MICS band is from 402MHz to 405MHz, and 10 channel space (every channel has 300KHz bandwidth) would be switched for data communicating.
    This work proposes a fractional-N phase-locked loop (PLL) circuit that is implemented with active inductors and auto-calibration technology. This PLL circuit achieves smaller chip area and provides wider range of the output frequency. To decrease the area of chip greatly, the active inductors and the capacitors of the loop filter are implemented with MOS-FET. Moreover, the proposed auto-calibration technique would reduce and overcome the effect of the voltage、temperature and process variations. The measurement results have shown that the proposed Fractional-N PLL chip, with a die size of 450 385 um2, achieves phase noise @ 1MHz of -105.5dBc/Hz, operating frequency range from 218 MHz to 466 MHz, and power consumption of 5.13 mW at 402MHz (excluding output buffer). This work is fabricated in TSMC 0.18 μm 1P6M CMOS process technology.

    第一章 緒論 1 1.1 研究動機與目的 1 1.2 研究方法與步驟 3 1.3 論文組織 3 第二章 鎖相迴路先前技術探討 4 2.1 鎖相迴路種類介紹 4 2.1.1 線性式鎖相迴路(Linear Phase Lock Loop)4 2.1.2 全數位式鎖相迴路(All Digital Phase Lock Loop)5 2.1.3 電荷幫浦式鎖相迴路(Charge Pump Phase Lock Loop)5 2.2 各式振盪器比較 6 2.2.1 環形振盪器(Ring Oscillator)6 2.2.2 被動式電感LC諧振電路(Passive Inductor LC Tank)6 2.2.3 主動式電感LC諧振電路(Active Inductor LC Tank)7 2.3 自動校正機制 7 2.4 頻率合成器架構 10 第三章 和差調變器 11 3.1 和差調變器基本原理 11 3.2 和差調變器基本架構 11 3.2.1 ㄧ階和差調變器 11 3.2.2 二階和差調變器 13 3.2.3 三階和差調變器 14 3.3 加入雜訊擾動 17 第四章 系統設計與行為模擬 20 4.1 PLL子電路Simulink模擬 20 4.1.1 相位頻率偵測器(PFD) 20 4.1.2 電荷幫浦(CP) 23 4.1.3 迴路濾波器(LPF) 25 4.1.4 PFD+CP+LPF 27 4.1.5 壓控振盪器(VCO) 29 4.1.6 除頻器(FD) 31 4.2 PLL整體電路Simulink模擬 32 第五章 非整數式鎖相迴路電路設計 34 5.1 系統規格與應用頻段 34 5.2 非整數式鎖相迴路架構 35 5.3 相位頻率偵測器電路架構 36 5.3.1死區(Dead Zone) 36 5.3.2 D Flip-Flop 37 5.3.3相位頻率偵測器電路 38 5.4 電荷幫浦電路架構 39 5.4.1電荷幫浦設計考量 39 5.4.2電荷幫浦電路 41 5.5 迴路濾波器電路架構 44 5.5.1 MOS電容 44 5.5.2 三階迴路濾波器 45 5.6 壓控振盪器電路架構 47 5.6.1相位雜訊 47 5.6.2可變電容 48 5.6.3壓控振盪器電路 50 5.7 除頻器電路架構 53 5.8 自動校正機制架構 54 5.9 模擬驗證(Pre-layout simulation) 56 5.10 結論與比較 62 第六章 晶片佈局與量測 64 6.1 晶片佈局考量 64 6.2 晶片佈局 64 6.2.1相位頻率偵測器佈局 65 6.2.2電荷幫浦佈局 66 6.2.3迴路濾波器佈局 66 6.2.4壓控振盪器佈局 67 6.2.5除頻器佈局 67 6.2.6校正機制電路佈局 68 6.2.7和差調變器佈局 69 6.2.8佈局平面圖 71 6.3 佈局後模擬驗證(Post-layout simulation) 73 6.4 量測考量 81 6.5 量測結果 84 6.5.1單一鎖相迴路量測結果 84 6.5.2非整數式鎖相迴路量測結果 91 第七章 總結與未來展望 96 7.1總結 96 7.2未來展望 97 References 98

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