研究生: |
吳俊杰 Wu, Chun-Chieh |
---|---|
論文名稱: |
應用於植入式醫療通訊頻段之非整數式鎖相迴路 A Fractional-N PLL for MICS Band Application |
指導教授: |
羅錦興
Luo, Ching-Hsing |
共同指導教授: |
黃弘一
Huang, Hong-Yi |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 中文 |
論文頁數: | 100 |
中文關鍵詞: | 電壓控制振盪器 、非整數式鎖相迴路 、主動式電感 、自動校正機制 |
外文關鍵詞: | Voltage control oscillator, Fractional-N PLL, Active inductor, Calibration |
相關次數: | 點閱:90 下載:1 |
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在現今的無線通訊系統上,頻率合成器擁有著相當重要的位置,並且隨著不同的應用頻段會有著不同的規格需求。在本論文中是針對一個應用於生醫植入式通訊系統(Medical Implantable Communication System, MICS)的頻段來做應用與設計,而此系統應用頻段為,402MHz~405MHz且channel space 為300KHz擁有十個頻段可供切換。
而非整數式鎖相迴路則是實現頻率合成器的方式之ㄧ,在本論文中提出使用主動式電感與自動校正機制之非整數式鎖相迴路,此電路提供了一較寬的輸出頻率範圍避免因振盪器的漂移導致電路工作不正常以及較小的晶片面積需求。利用了主動式電感降低被動電感的面積需求以及迴路濾波器之電容皆使用MOS替代,可大幅度的降低對MIM電容面積的浪費與成本。在配合上自動校正機制,可盡量避免製程、溫度、電壓變異所造成的影響。非整數式鎖相迴路晶片的製作是利用台積電0.18-um 1P6M之製程所製作,其操作頻率為218-MHz到466-MHz,phase noise @ 1MHz 為-105.6dBc/Hz。整體晶片的面積為825 730 um2(中心電路:450 385 um2),操作頻率402-MHz時,其功率消耗約為5.13 mW(不含output buffer)。
The frequency synthesizer circuit is an important part of wireless communication system. Due to different communication applications, the requirements of the frequency synthesizer specifications are also dissimilar. In this work, the frequency synthesizer circuit is designed for Medical Implantable Communication System (MICS) application. The operating range of MICS band is from 402MHz to 405MHz, and 10 channel space (every channel has 300KHz bandwidth) would be switched for data communicating.
This work proposes a fractional-N phase-locked loop (PLL) circuit that is implemented with active inductors and auto-calibration technology. This PLL circuit achieves smaller chip area and provides wider range of the output frequency. To decrease the area of chip greatly, the active inductors and the capacitors of the loop filter are implemented with MOS-FET. Moreover, the proposed auto-calibration technique would reduce and overcome the effect of the voltage、temperature and process variations. The measurement results have shown that the proposed Fractional-N PLL chip, with a die size of 450 385 um2, achieves phase noise @ 1MHz of -105.5dBc/Hz, operating frequency range from 218 MHz to 466 MHz, and power consumption of 5.13 mW at 402MHz (excluding output buffer). This work is fabricated in TSMC 0.18 μm 1P6M CMOS process technology.
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