心血管疾病與瓣膜疾病一直都帶來許多健康危害，心電訊號可以用來檢測心血管疾病而心音則可以用來評估瓣膜狀況，結合兩種訊號更可以幫助醫生聽診更加迅速，也讓醫學生在學習聽診時，更快上手。本篇論文將以同步心音心電之智慧聽診器系統為核心，闡述其特點與設計理念，並將系統應用於臨床試驗與心音分析。
本系統可分為訊號監測裝置、心音分析演算法與使用者介面(智慧型裝置應用程式)，其中前端監測裝置有聽診器與心電監測裝置，分別收集心音與心電訊號，演算法則包含訊號同步演算法、心音辨識與心雜音偵測演算法，心音辨識演算法可以辨識第一心音與第二心音，將其應用在正常心音上辨識率可達100%，將其應用在換有心雜音患者的心音上，其辨識率則有96.7%，而心雜音偵測演算法可以檢測是否患有收縮期雜音，其準確率有95.1%，此外針對使用者介面開發了智慧裝置應用程式，最後更是近一步將此部分演算法硬體化，採用TSMC 0.18μm standard CMOS 製程進行設計與製作，使邊緣運算應用於本系統之中，加速辨識速度。

People suffered from cardiovascular diseases and valvular heart diseases are increased in recent years. However, cardiovascular diseases can be detected by ECG while valvular heart diseases should be detected by heart sound. With two of the bio-signals combining together in synchronization, it can accelerate auscultation and learning auscultation. The study of this thesis is based on the smart stethoscope system with synchronized heart sound and ECG and its application of clinical trials to reveal cardiovascular diseases. The contents cover every concept used in the system including medical devices, bio-signals, sensors, front-end circuitry, algorithms, machine learning techniques, and the final chip design concerns.
The system combines bio-signal monitoring devices, heart sound analysis algorithms, and a user interface on smart devices (APP) to demonstrate the clinical trial. There are two monitoring devices in the system, the Stethoscope and ECG patch, recording heart sound and ECG signal respectively. As for algorithms, there are 3 algorithms in the system. First is the synchronized algorithm is proposed to align heart sound and ECG at the same timing. Secondly, the heart sound classifying algorithm is used to distinguish S1 and S2. The accuracy for heart sound classification applying on normal heart sound reaches 100% while its accuracy for heart murmurs is 96.7%. Thirdly, the heart murmur detection can detect the systolic murmur and the macro f1 score is 95.1%. The smart device APP with a friendly interface for users is implemented for monitoring the heart sound and ECG signal in real-time. Finally, the proposed algorithm is implemented by hardware with a 0.18 µm standard CMOS process to demonstrated the concept of edge computing. The algorithm in the chip is built by the machine learning technique to speed up the machine learning.

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