本論文實現了單軸電容式加速度感測器，並把前端感測器與後端訊號處理電路結合在同一顆晶片中，感測器包含了四個版本，其中有兩個版本能成功偵測加速度:第一版本感測加速度應力之效果最好，在±13g的感測範圍下有35.57 (mV/g)的靈敏度，消耗功率為0.561mW；第四版本在±3g的感測範圍下最高有45.4 (mV/g)的靈敏度，消耗功率約在0.5676mW。在電路部分的主要貢獻，是實現了具抑制直流位準放大的雙端轉單端差分差動放大器，以避免輸出訊號在高放大倍率時飽和。
晶片採用台積電 (TSMC) 0.35 μm CMOS/MEMS 2P4M 3.3 V 混合訊號製程加上微機電後製程製作，以40 S/B 封裝，晶片面積為2.1282×2.4972mm2，含四組感測器與四組相同之後端處理電路。

Four different structures of single-axis capacitive accelerometers are designed and implemented in this thesis. The four front-end sensors and their back-end signal processing circuits are integrated into a single chip, and two of them (the 1st and 4th accelerometer) are functional work. According to the measurement results, the 1st accelerometer has the best sensitivity, which is 35.57 mV/g with a full range of ±13 g, and its power consumption is around 0.561 mW. The 4th one has a maximum sensitivity of 45.4 mV/g with a sensing range of ± 3, and its power consumption is around 0.5676 mW. In addition, the main contribution of the post-processing circuits is to propose a differential-to-single-end differential difference amplifier (DDA) with dc bias voltage suppression, which amplifies the input differential signal only without amplifying its dc bias voltage, and it prevents the output from saturation.
The proposed chip was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 μm CMOS/MEMS 2P4M 3.3 V/5 V process and MEMS post process. The die area of this chip is 2.1282 mm × 2.4972 mm

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