本論文中，我們主要研究由矽鍺/矽異質接面所產生的應變機制對電晶體元件電特性的提升。我們先後利用固體源分子束磊晶法，與超高真空化學氣相沉積法，成長一系列矽鍺/矽異質接面場效電晶體結構，並針對各種結構進行能帶工程以及載子分布理論模擬分析。
在實驗製作方面，我們首先研製出應變矽鍺通道摻雜金半場效電晶體，改善一般調變摻雜電晶體閘極電壓擺幅較小的缺點。我們並加入平面摻雜技術，以提高載子侷限能力，由實驗結果得知，通道摻雜電晶體的確顯示出較佳的線性度，且平面摻雜也有著較佳的汲極電流與轉導特性。
接著，我們進一步開發適用於當今極大型積體電路的P型應變矽鍺金氧半場效電晶體。由於一般的結構在矽鍺通道上必須磊晶一層矽覆蓋層改善半導體與二氧化矽的介面特性，因此我們首先研究此矽覆蓋層厚度對元件電特性的影響。接著我們將漸變式通道的觀念引進到矽鍺通道中。最後我們使用雙矽鍺通道結構改善元件的閘極電壓擺幅。
由許多文獻中可以得知，應變矽的N型金氧半場效電晶體可以很有效地提昇電子的漂移率，加上我們的研究顯示，應變矽鍺P型金氧半場效電晶體可以提高電洞的漂移率。因此，我們試著將應變矽鍺之P型金氧半場效電晶體與應變矽之N型金氧半場效電晶體製作於同一片晶片上，開發出新式的互補式金氧半場效電晶體。我們使用各別製作的方式，分開P型與N型電晶體元件結構的製作，如此可以分別去設計兩者最佳的結構參數。實驗結果顯示，新式的互補式金氧半場效電晶體的結構的確有著比純矽互補式金氧半場效電晶體更佳的特性。
可靠度是元件另一個重要的參數，因此，最後我們探討矽鍺元件的可靠度分析。我們研究P型電晶體的負偏壓溫度效應。負偏壓溫度效應主要是電洞打斷矽與二氧化矽介面的矽氫鍵結，產生介面陷阱並進而影響元件的臨限電壓。由於應變矽鍺元件會將大部分的電洞載子侷限在埋藏通道中，降低矽與二氧化矽介面的濃度。因此矽鍺P型場效電晶體有較小的負偏壓溫度不穩定性效應。也較適合之後的積體電路使用。

In this dissertation, the study of strain engineering on device performances is reported. A series of SiGe/Si FET structures grown by solid-source molecular beam epitaxy (SS-MBE) or ultra high vacuum chemical vapor deposition (UHV-CVD) are presented. Besides, the simulation of band engineering and carrier distribution for devices has been conducted.
Firstly, the fabrication and characterization of strained-SiGe doped-channel PMESFETs are proposed to achieve higher device linearity. The devices structure combines the advantages of SiGe material and δ-doped technique to increase carrier confinement. As observed from the experiment results, it is found that δ-doped-channel structure exhibits not only better device linearity but also higher current drivability.
Secondarily, we developed compressive strained SiGe PMOSFETs which are suitable for the ULSI technology. The structure parameter such as Si-cap thickness, Ge profile in the SiGe-conducting channel and spacer thickness between double SiGe channels are estabilished and discussed.
Thirdly, we developed two novel CMOS architectures that use tensile stress which induced by the Si nitride-capping layer or SiGe virtual substrate, together with the pseudomorphic compressive stress in SiGe layer to improve the drive current of both n- and pMOSFETs simultaneously. The unique advantage of this process flow is that on the same wafer, individual MOSFET performance can be adjusted independently to their optimum due to the separation process for two type devices. It is found that n- and pMOSFET in both novel CMOS architectures behaved better performance, not only higher drain-to-source saturation current but also higher transconductance than the Si-control devices, thus making this flow to show a great flexibility for developing next-generation high-performance CMOS.
Finally, the negative bias temperature instability (NBTI) effect on SiGe devices has been investigated. NBTI effect is mainly from the break of Si-H bonds caused by hot hole at Si/SiO2 interface and will generate interface traps which affect the threshold voltage. By introduction of strained SiGe layer in PMOSFET, the holes are primarily located in the SiGe channel due to valence band offset and thus the hole concentration in Si surface channel is lower than that of control Si PMOSFET. Therefore SiGe PMOSFETs have lower NBTI effect compared with control Si devices. The experimental results show that SiGe devices are better choices for the future ULSI technology.

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