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研究生：	何嘉銘 Ho, Chia-Ming
論文名稱：	嶄新低功耗及低成本之掃描測試技術 Novel Scan Techniques for Low Power and Low Cost Testing
指導教授：	李昆忠 Lee, Kuen-Jong
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	68
中文關鍵詞：	低成本測試、低功率測試、掃描測試
外文關鍵詞：	Scan-based testing, Low cost testing, Low power testing
相關次數：	點閱：96 下載：1
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　　超大型積體電路技術的發展使得晶片複雜度日益提升。為了加強晶片的可測性，掃描技術是一種最廣為使用的測試方法。然而，採用此技術面臨兩項極為嚴重的問題－大量的功率消耗及測試成本。其中，測試成本又可概分為三個主要因素，分別為測試時間、測試資料量以及掃描輸入接腳數。
　　
　　為了解決掃瞄技術面臨的兩項問題，在降低功率消耗方面，我們採用多重擷取順序的方法，有效的降低平均功率及尖峰功率消耗。並提出一個高效率的測試向量產生程序，縮短產生測試向量的時間。
　　
　　另外，我們提出一種嶄新的掃描測試技術，可大幅度降低測試時間、測試資料量以及功率消耗。此技術之主要觀念在於利用掃描暫存器間”共享”的特性，在單一輸入線之條件下將其建構成多條掃描鏈，且能保有完整的錯誤涵蓋率。在允許的測試機台輸入線之環境下，此技術亦能延伸至多條掃描輸入線之架構。在此架構之下，我們提供一種能降低測試功率消耗之技術。根據ISCAS89電路實驗結果所示，在單一輸入線的架構下，此方法可降低測試時間及測試資料量達90%以上，並可降低測試功率達96.3%。
　　
　　綜合以上所述，我們可以有效的降低功率消耗且在不增加額外輸入接腳數的情況下降低測試時間及測試資料量，因而達到降低功率消耗及測試成本之兩項目標。

　With the progress of very large scale integration (VLSI) techniques, the circuit complexity increases dramatically. To enhance the testability of the circuit, many design for testability (DFT) techniques are developed. Scan technique is one of these techniques and is widely used in industry. However, excess power dissipation and large test cost are two critical problems of scan testing. The test cost is composed of three main factors, namely test application time, test data volume and the number of test pins.
　　
　In the power aspect, recently the multiple capture orders technique has been used to reduce both average and peak power dissipation. The technique, however, requires long test generation time. In this thesis, we propose a modified test pattern generation procedure to shorten the test pattern generation time.
　　
　Furthermore, we propose a novel scan technique to reduce the test application time, test data volume, and test power dissipation simultaneously. The basic idea is to analyze the compatibility of scan flip-flops and construct multiple scan chains with single scan input without any fault coverage degradation. This technique can be directly applied to the configuration of multiple scan inputs according to the number of available test channels. Besides, we also give a low power technique applied to our scan architecture. Experimental results for large ISCAS’89 benchmark circuits show that with single scan input, the proposed method can reduce the test application time and test data volume by 90%, and reduce power dissipation by 96.3% in average compared with conventional scan methodology.
　　
　As described above, we can efficiently reduce the test power dissipation and can reduce the test application time and test data volume without extra test pins. Hence, the two critical problems of scan testing can be solved.

Chapter 1 Introduction......................................................1
1.1 Problem Description.....................................................1
　1.1.1 Test Power Consumption...............................................2
　1.1.2 Test Volume, Test Application Time, and Test Pins....................2
1.2 Introduction to the Proposed Techniques.................................3
1.3 Organization of Thesis..................................................4
Chapter 2 Previous Work.....................................................6
2.1 Test Power Reduction....................................................6
2.2 Test Volume and Test Time Reduction....................................10
Chapter 3 Multiple Capture Orders Technique with Essential Fault Concept...14
3.1 Review the technique of Multiple Capture Orders........................15
3.2 Test Architecture......................................................19
3.3 Modified Approaches....................................................21
　3.3.1 Essential Fault Concept for Efficient Test Generation...............22
　3.3.2 Consideration for Reverse Order Capture Operation...................24
3.4 Experimental Results...................................................24
　3.4.1 Power Dissipation Model.............................................25
　3.4.2 Test Generation Results of Two Procedures...........................25
　3.4.3 Experimental Results of Single Scan Architecture....................27
　3.4.4 Experimental Results of Multiple Scan Architecture..................30
　3.4.5 Comparison..........................................................33
Chapter 4 Broadcasting Techniques for Multiple Scan Chains.................36
4.1 Overview of the Proposed Method........................................37
4.2 Build Incompatibility Graph............................................38
4.3 Balance Coloring Procedure.............................................41
4.4 Construct Broadcasting Scan Architecture...............................43
4.5 Low Power Consideration................................................47
　4.5.1 Compatible Groups Ordering..........................................47
　4.5.2 Scan-in/Scan-out Identification.....................................49
4.6 Routing Distance Consideration.........................................51
4.7 Experimental Results...................................................52
　4.7.1 Experimental Results of Single Scan-In Configuration................53
　4.7.2 Experimental Results of Multiple Scan-In Configuration..............56
Chapter 5 Conclusions......................................................62
Reference	..................................................................64
                                    

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