近年来，深度神經網路 (DNN) 算法已經成為人工智能 (AI) 計算的主流。人工智能運算需求的激增需要高性能的DNN演算法硬體加速器，例如，Cerebras的晶圆級引擎 (WSE)使用一整片的晶圓來創建世界上最大的晶圓級人工智能晶片。在這篇論文中，我們推測在未来，3D晶圓級高性能計算 (HPC) 系统將被開發出來，其中兩片晶圆 (2D晶片) 堆疊在一起，形成一個巨大的3D晶片，通過Through Silicon Via (TSV) 垂直連接。然而，為了讓這種3D晶片成為可能，我們必須在晶圓堆疊後维持晶片的良率。在最初的WSE晶片中，已經採用了冗餘修復方法来提高2D晶片的良率。在本文中，在2D冗餘修復方法的基礎上，我們提出了一種三维冗餘修復方法，該方法利用了一種新穎的晶圓匹配方法和測試修復流程。實驗结果表明，我們的晶圓匹配方法可以提高三維晶圓堆疊晶片的良率。

In recent years, deep neural network (DNN) algorithms have become the mainstream of artificial intelligence (AI) computing. The burst in AI computing needs calls for high-performance hardware accelerators for DNN algorithms, e.g., the Wafer Scale Engine (WSE) from Cerebras uses the full wafer to create the world’s largest wafer-scale AI chip. In this paper, we conjecture that in the future, the 3D wafer-level high-performance computing (HPC) system will be developed, where two wafers (2D chips) are stacked to form a monstrous 3D chip, connected vertically by the through-silicon vias (TSVs). To make such 3D chips possible, however, we will have to maintain the yield of the chips after the wafers are stacked. In the original WSE chip, a redundancy repair scheme has already been adopted for improving the yield of the 2D chips. In this paper, on top of the 2D redundancy repair scheme, we propose a 3D redundancy repair scheme, which takes advantage of a novel wafer-matching method and a test and repair flow. Experimental results show that our wafer-matching method can improve the yield of the 3D wafer-level chips.

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