| 研究生: |
程亞淇 Cheng, Ya-Chi |
|---|---|
| 論文名稱: |
以決策樹模型的篩選方法改善記憶體晶片的測試品質 Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method |
| 指導教授: |
謝明得
Shieh, Ming-Der |
| 共同指導教授: |
吳誠文
Wu, Cheng-Wen |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2022 |
| 畢業學年度: | 110 |
| 語文別: | 英文 |
| 論文頁數: | 30 |
| 中文關鍵詞: | 決策樹 、高溫壽命試驗 、晶片測試 、機器學習 、記憶體 、品質 、可靠度 、壓力測試 |
| 外文關鍵詞: | decision tree, HTOL test, IC testing, machine learning, memory, quality, reliability, stress test |
| 相關次數: | 點閱:59 下載:5 |
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現今,對於高可靠度和高品質積體電路 (IC) 產品的需求不斷增加,同時它們的測試成本應盡可能地保持越低越好。我們研究了先進記憶體晶片的測試流程,其中高溫壽命試驗 (high temperature operating life test) 已被用於確定晶片的內在可靠度。這種高溫抽樣試驗將運行 168到 1000 小時,因此它非常地耗時及昂貴。近年,只要可以取得良好的訓練資料,機器學習 (machine learning) 算法就可以被用於解決分類問題。在我們的例子中,已經從現有測試流程中收集到大量的參數測試數據。因此,在本篇論文中,為了預測不會通過高溫壽命試驗的失效(不可靠)晶片,我們提出了一種基於決策樹模型 (decision tree) 的篩選方法。並且我們表明經驗豐富的測試工程師可以決定參數測試數據的優先順序,以便更好地使用及建構決策樹模型。最後,我們利用決策樹模型的高可解釋性來開發多特徵啟發式 (multi-feature heuristics),而這些啟發式可用於提高最終測試 (final test) 的測試品質。當我們將過度誤殺率(overkill rate) 維持在0% 時,在5奈米記憶體的實驗中,我們的多特徵啟發式可以多篩選出25% 的失效記憶體 (SRAM) 晶片,而在4奈米記憶體的實驗中,我們的多特徵啟發式可以多篩選出14%的失效記憶體 (SRAM) 晶片。因此,我們可以在不增加額外成本的情況下改善最終測試的測試品質。
There is a growing demand for high-reliability and high-quality integrated circuit (IC) products, while their test costs should be kept as low as possible. We investigate the test process of advanced memory chips, where the high temperature operating life (HTOL) test has been used to determine their intrinsic reliability. This high temperature sampling test can run from 168 to 1,000 hours, so it is time-consuming and expensive. Recently, machine learning (ML) algorithms have been used to solve classification problems, so far as good training data can be obtained. In our case, there is already a large amount of parametric test data generated from the existing test flow. Therefore, in this work, we propose a decision tree (DT)-based screening method to predict weak (unreliable) dies that would fail the HTOL test. We show that experienced test engineers can prioritize the parametric test data for better use of the DT model. Finally, we take advantage of the high interpretability of DT to develop the multi-feature heuristics, which can be used to improve the quality of final test (FT). Keeping the overkill rate at 0%, we can screen out 25% more bad dies in the 5nm SRAM case with the heuristics, and in the 4nm case, we can screen out 14% more bad dies, i.e., we can improve the FT quality without additional cost.
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