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研究生： 劉純成
Liu, Chun-Cheng
論文名稱： 高速低耗能逐漸趨近式類比至數位轉換器之設計
Design of High-Speed Energy-Efficient Successive-Approximation Analog-to-Digital Converters
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 91
中文關鍵詞： 逐漸趨近式 、類比至數位轉換器
外文關鍵詞： SAR ADC
相關次數： 點閱：150  下載：72 
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    • 本論文提出三個應用於逐漸趨近式類比至數位轉換器的電路設計技術，並且透過實際的晶片下線和量測驗證，證實所提出之電路設計技術可以有效提升電路的操作速度以及降低每次轉換所消耗的能量。所提出的電路設計技術以及晶片實作成果簡述如下：
    第一個技術為單調式的電容切換機制，其比傳統架構的切換方式節省約81.3%的切換能量以及50%的取樣電容。在0.13微米互補式金氧半電晶體製程下，我們利用此技術來實現一個10位元，每秒5千萬次取樣的逐漸趨近式類比至數位轉換器。此類比至數位轉換器在1.2伏特的電壓下，其功率消耗為0.92毫瓦，有效位元為8.48 bits，等效的FOM僅為52 fJ/conversion-step。然而，單調式的電容切換機制會導致比較器輸入端訊號共模電壓的改變，使得比較器的動態偏移嚴重影響電路的效能。為了改善這個問題，我們提出一個改良版的比較器電路，可以有效控制比較器的動態偏移量。此外，在電路內部改採用非同步操作方式以避免使用數倍於取樣速度的高頻時脈訊號，降低系統整合的複雜度。同樣在0.13微米互補式金氧半電晶體製程下，我們實現另一個10位元，每秒5千萬次取樣的逐漸趨近式類比至數位轉換器。在1.2伏特的電壓下，其功率消耗為0.826毫瓦，有效位元提升為9.18 bits，等效的FOM僅為29 fJ/conversion-step。
    第二個技術為二進制的錯誤補償機制。高速操作的逐漸趨近式類比至數位轉換器，由於每個位元週期的時間非常短，常常在DAC電壓還沒穩定的時候就必須要做下一次的比較，DAC電壓穩定的問題嚴重影響電路的效能，也限制了電路的操作速度。我們提出了一個二進制的錯誤補償機制，在電路中插入額外的補償位元來做錯誤校正，因此比較器可以在DAC還沒穩定的時候先做比較，以提升電路操作速度。在65奈米互補式金氧半電晶體製程下，我們利用此技術來實現一個10位元，取樣速度可以達到每秒1億次的逐漸趨近式類比至數位轉換器。在1.2伏特的電壓下，其功率消耗為1.13毫瓦，有效位元為9.51 bits，等效的FOM僅為15.5 fJ/conversion-step。
    第三個技術則是利用一個輔助預測電路，來避免不必要的電容切換，此技術可以省下40-45%的電容切換能量消耗。配合第一個技術，電容切換的能量消耗可以比傳統方法減少約90%左右。除此之外，這個技術還能改善電路的靜態以及動態效能。在0.18微米互補式金氧半電晶體製程下，我們利用此技巧來實現一個10位元，每秒1千萬次取樣的逐漸趨近式類比至數位轉換器。在1伏特的電壓下，其功率消耗僅為98微瓦，有效位元為接近理想的9.83 bits，等效的FOM僅為11 fJ/conversion-step。

    This dissertation proposes three circuit design techniques for successive-approximation register (SAR) analog-to-digital converters (ADCs). According to the measurement results of the proof-of-concept prototypes, the proposed techniques are able to improve the operating speed and achieve excellent energy efficiency. The proposed techniques and chip measurement results are sketched as follows:
    The first technique is a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total sampling capacitance are reduced by about 81.3% and 50%, respectively. A 10-bit, 50-MS/s SAR ADC with the proposed monotonic capacitor switching procedure is implemented in a 0.13-µm 1P8M CMOS technology. The prototype ADC consumes 0.92 mW from a 1.2-V supply, and the effective number of bit (ENOB) is 8.48 bits. The resulting figure of merit (FOM) is 52 fJ/conversion-step. However, the signal-dependent offset caused by the variation of the input common-mode voltage degrades the linearity of ADC. We proposed an improved comparator design to avoid the linearity degradation. Besides, to avoid a clock signal with frequency higher than sampling rate, we used an asynchronous control circuit to internally generate the necessary control signals. The revised prototype is also implemented in a 0.13-µm 1P8M CMOS technology. It consumes 0.826 mW from a 1.2-V supply and achieves an ENOB of 9.18 bits. The resultant FOM is 29 fJ/conversion-step.
    The second technique is a binary-scaled error compensation method. In a medium-to-high resolution case, the DAC settling issue limits the operating speed of a SAR ADC, because it is not easy for the capacitive DAC to stabilize in a short time interval. We insert extra binary-scaled compensation bits to compensate for the DAC settling error. Accordingly, the comparator can perform comparison before the DAC is completely settled, resulting in improved operating speed. A 10-bit, 100-MS/s SAR ADC using the binary-scaled error compensation method is implemented in a 65-nm 1P6M CMOS technology. The prototype consumes 1.13 mW from a 1.2-V supply and achieves an ENOB of 9.51 bits. The resultant FOM is 15.5 fJ/conversion-step.
    The third technique is a predictive capacitor switching method that uses a predictive circuit to avoid unnecessary switching in a DAC network. This method saves 40~45% switching energy. Combined with the first technique, the average switching energy is reduced by about 90% than the conventional one. In addition, this technique improves static and dynamic performance of a SAR ADC. A 10-bit, 10-MS/s SAR ADC using this method is implemented in a 0.18-µm 1P6M CMOS technology. The prototype consumes 98 µW from a 1-V supply and achieves an excellent ENOB of 9.83 bits. The resultant FOM is only 11 fJ/conversion-step.

    Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the dissertation 5 Chapter 2 Monotonic Capacitor Switching Procedure for SAR ADC 6 2.1 Proposed Monotonic Capacitor Switching Procedure 7 2.1.1 Conventional SAR ADC 7 2.1.2 Proposed SAR ADC 8 2.1.3 Analysis of Switching Energy in DAC Network 11 2.2 A 0.92MW 10-BIT 50-MS/S SAR ADC 15 2.2.1 Sample and Hold Circuit 15 2.2.2 Comparator Design 17 2.2.3 SAR Control Logic 18 2.2.4 Capacitor Array 20 2.2.5 Measurement Results 21 2.3 A 10-bit 50-Ms/S SAR ADC with an Improved Comparator Design 25 2.3.1 S/H circuit 25 2.3.2 Dynamic Comparator with a Current Source 26 2.3.3 SAR Control Logic 28 2.3.4 Unit Capacitor 29 2.3.5 Measurement Results 30 2.4 A 6-bit 220-MS/s Time-Interleaving SAR ADC 37 2.4.1 Architecture 37 2.4.2 Comparator Design 39 2.4.3 SAR Control Logic 39 2.4.4 Unit Capacitor 40 2.4.5 Layout and Floorplan 41 2.4.6 Measurement Results 42 2.5 Summary 46 Chapter 3 Binary-Scaled Error Compensation Method for High-Speed SAR ADC 47 3.1 Introduction 47 3.2 The Proposed Binary-Scaled Error Compensation Method 48 3.2.1 Conventional Binary Search 48 3.2.2 Non-binary Search 50 3.2.3 Proposed Binary Search with Error Compensation 51 3.3 A 10-bit 100-MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation 53 3.3.1 Architecture 53 3.3.2 Digital Error Correction Logic 54 3.3.3 Measurement Results 56 3.4 Summary 61 Chapter 4 Predictive Capacitor Switching Procedure for SAR ADC 62 4.1 Introduction 62 4.2 Splitting Monotonic Capacitor Switching Procedure 63 4.3 Predictive Capacitor Switching Procedure 65 4.4 A 1-V 11 fj/Conversion-Step 10-bit 10-MS/s Asynchronous SAR ADC 68 4.4.1 Architecture 68 4.4.2 Discussion on DAC Settling 71 4.4.3 Matlab Simulation Result 73 4.4.4 Measurement Results 75 4.5 Summary 81 Chapter 5 Conclusions and Future Work 82 5.1 Conclusions 82 5.2 Future Work 84 Reference 85 Publication List 89 Biography 91

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