近年來隨著高速運算以及人工智能的需求，除了推進演算法，對於硬體元件的設計與開發需求更是蒸蒸日上，為了在這個逼近摩爾定律極限的時代持續的微縮晶片體積，人們開始不僅在單一元件大量的採用堆疊式結構，如堆疊式奈米薄片、奈米線以及堆疊式互補場效電晶體，也在不同功能晶片間使用堆疊的方式節省面積以及減少訊號延遲，從而實現系統單晶片系統，目前大部分的系統單晶面都是採納矽穿孔以及黏晶技術來垂直整合不同功能的晶片，如邏輯閘、記憶體及射頻元件等等，為了持續增加元件積集度、減少延遲與節省成本，一體化製程三維積體電路被視為非常具有潛力的一項技術，其概念為取代黏晶以及矽穿孔技術，直接在單晶邏輯閘最高密度的第一層以上進行後段的各項元件製作，此論文即為專注以堆疊式互補場效電晶體為基礎概念開發各項重要元件，包含反相器、靜態隨機存取記憶體、嵌入式快閃記憶體與射頻元件於後段低溫製程中。
通篇論文以兩種堆疊式互補場效電晶體結構為主軸，首先是共閘極無接面全包覆式堆疊奈米薄片互補場效電晶體，以該結構實現之反相器為全球首顆實證的堆疊式反相器，在文中我們詳細的討論的各項重要參數對單一元件表現及轉移特性曲線的影響，包含了通道尺寸、通道個數、離子佈植條件、汲極源極厚度與金屬後處理，本論文已提出了以該結構為原型製作嵌入式快閃記憶體與射頻元件的製程，並以TCAD模擬其行為並優化符合不同需求之特性。第二種結構則是異質通道材料整合之堆疊式互補場效電晶體，其亦為全球首顆實證之異質堆疊式反相器，本研究以該結構整合N型非晶質氧化銦鎵鋅於P型多晶矽電晶體之上，其結構特性為將上下層通道的介面以及堆疊閘極因應其自身需求分別處理，同時能免除上層通道移除下方犧牲層後坍塌與被破壞的可能性，本研究亦針對結構中不同參數討論其對單一元件表現及轉移特性曲線的影響，而且因為其閘極結構的特殊性，其至多可以擁有三個閘極，一個控制閘極主導整體反相器操作，其他二者調變閘極分別能改變上下層電晶體的電流大小與臨界電壓達到針對不同操作需求可優化的彈性，本論文只演示了控制閘極以及上層調變閘極，並以靜態隨機存取記憶體來演示調變閘極的功能。在製作該異質堆疊式反相器的同時，有著P型多晶矽保護環的近閘極全包覆式N型非晶質氧化銦鎵射頻元件亦能被製作於同一基板上，本研究詳盡地討論了結構對電容以及頻率的影響，並製作出超過1 GHz的氧化物電晶體射頻元件。
本論文為所有製程皆低於600 ℃，表示所有元件都符合低溫製程的熱預算需求，對後續製作堆疊於後段製程之元件非常有利，可視為實現一體化製程單晶片系統及系統級面板的潛力選項，並提供未來製程以及元件種類的多元性及可調性。

In recent years, with the demand for high-speed computing (HPC) and artificial intelligence (AI), besides advancing algorithms, there has been a growing need for the design and development of hardware components. In order to continue shrinking chip sizes in this era approaching the limits of Moore's Law, people have begun not only adopting stacked structures in large quantities for individual devices, such as stacked nanosheets, nanowires, and complementary field-effect transistors (CFET), but also bonding different functional chips to save area and reduce latency, thereby achieving system on a chip (SoC). Currently, most SoC designs adopt through-silicon via (TSV) and bonding techniques to vertically integrate different functional chips, such as logic gates, memory, and radio frequency devices. For further increasing device density, reducing latency, and saving costs, monolithic three-dimensional integrated circuits (M3D-IC) are regarded as a highly promising technology. The concept is to replace TSV and bonding technologies, and directly fabricate various functional devices above the highest-density logic gates in the first layer with a backend low-temperature process. This paper focuses on developing various important devices based on the concept of CFET, including inverters, static random-access memories (SRAMs), embedded flash memories (eFlash), and radio frequency (RF) devices in the backend with low-temperature process.
The entire thesis revolves two main structures of CFET. Firstly, it introduces the common gate junctionless gate-all-around stacked nanosheet CFET (JL-GAA-NS CFET, also called as JL-CFET in the thesis). The inverter implemented by this structure is the first demonstrated stacked inverter. In the dissertation, we extensively discuss the effects of various important parameters on the performance of individual devices and transfer characteristic curves (VTC), including channel dimensions, fin number, ion implantation conditions, source/drain thickness, and post-metallization treatment. The thesis proposes the processes for fabricating embedded flash memories and radio frequency devices based on this structure and optimizes their behaviors through TCAD simulation to meet different requirements. The second structure involves hybrid CFET, also the first demonstrated hybrid stacked inverter. This study integrates n-type amorphous indium-gallium-zinc oxide (α-IGZO) on top of p-type polycrystalline silicon transistors. The structural characteristics involve treating the interfaces of the upper and lower channel layers and gate stack according to their respective requirements, thereby avoiding the collapse and damage possibilities after removing the sacrificial layer beneath the upper channel. The study also discusses the effects of different parameters on the performance of individual devices and VTC. Due to the special structure of its gate, it can have up to three gates, with one controlled gate dominating the operation of the overall inverter, and the other two adjusted gates respectively changing the current and threshold voltage of the upper and lower transistors to achieve flexible optimization for different operational requirements. The dissertation only demonstrates the controlled gate and upper adjusted gate, using SRAM to illustrate the function of the adjusted gate. Meanwhile, while fabricating the hybrid CFET, GAA-like n-type α-IGZO RF devices with n-type polycrystalline silicon guard rings can also be fabricated on the same substrate. This study systematically discusses the effects of the structure on capacitance and frequency and demonstrated oxide semiconductor RF devices over 1 GHz.
This thesis ensures that all processes are below 600 ℃, indicating that all devices meet the thermal budget requirements of low-temperature processes. This is highly advantageous for the subsequent fabrication of devices in the backend process, making it a potential option for realizing SoC and system-on-panel (SoP). It also provides versatility and tunability for future processes and devices.

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