現今大部分攜帶式裝置中都含有數位信號處理相關的應用，像是一些多媒體跟影像處理方面的設計，這些應用需要許多的運算資源並造成可觀的功率消耗，因此對於攜帶式裝置低功率的設計方式一直是有其必要的。在數位信號處理中時常需要處理時域頻域之間的轉換因此時常需要多重取樣率的的設計方式而同步資料流模型時常被用來描述含有多重取樣率的應用。在此篇研究中我們提出了一個合成流程可用來將以同步資料流描述的多重取樣率應用合成為一低功耗且使用少量的傳輸緩衝器並同時滿足特定的吞吐量的電路。因功耗最佳化屬於NP完全問題，我們的合成流程首先會使用全域非同步區域同步的架構以及自定時排程讓運算單元盡量運作在較慢的時脈頻率來優化運算單元的功率消耗，接著我們提出了一種混合式緩衝機制來優化傳輸單元的功率消耗。此混合式緩衝機制利用同步記憶單元來維持資料流的同步，接著插入少量的非同步緩衝器來協調橫跨時脈的資料傳輸。然而以上方法只能達到區域最佳化但並不能達到全域最佳化，因為當運算單元運作在較慢的時脈頻率之下可能會需要使用較大深度的非同步緩衝器導致較高的功率消耗，對於此問題我們則接著使用模擬退火法來去探索系統的各種組態，並試著找出運算單元以及傳輸單元之間一平衡組態以降低非同步緩衝器的深度使得整體系統功耗可以再降低。實驗結果以JPEG編碼器以及Intra Frame編碼器來驗證此方式的效果

Streaming Digital Signal Processing (DSP) applications such as multimedia and graphic processing are deployed in majority of mobile devices that highly desire low power design methodology. Such DSP applications usually employ time and/or frequency domain transformations that require multi-rate designs by nature. As the Synchronous Data Flow (SDF) has been widely used to model streaming multi-rate DSP applications, in this thesis we develop a synthesis method for multi-rate systems modelled by SDF graphs with the objective of minimizing the power consumption while satisfying the given throughput constraint and using as few communication buffers as possible. Owing to the NP-completeness nature of the problem, we propose a synthesis flow by first optimizing computation power using self-timed scheduling and Globally Asynchronous Locally Asynchronous (GALS) architecture. The buffer area and the consumed power are then optimized by using a novel hybrid synchronous/asynchronous buffering mechanism. This hybrid buffering mechanism employs synchronous memory to implement minimal size of buffer for data synchronization. It then inserts minimal asynchronous buffers to serve the purpose of Clock-Domain-Crossing (CDC) communication. However the above method may result in local but not global optimization because applying lowest possible clock rates over computation units first may result in bigger communication buffers and higher total power consumption. As such a simulated-annealing heuristic (SA) is used to explore the design space of the target system. By identifying a balanced configuration between computation components and communication buffers the SA further minimizes the total power. Experiments on a JPEG encoder and an Intra Frame encoder of an H.264 decoder have been done and the results validate the efficiency and effectiveness of the proposed method in dealing with multi-rate systems.

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