| 研究生: |
黃晧源 Huang, Hau-Yuan |
|---|---|
| 論文名稱: |
非晶態氧化銦鎵鋅薄膜電晶體元件工程開發與垂直式金屬基極電晶體之研製 Fabrication and Characterization of Amorphous InGaZnO Thin-Film and Metal-Base Transistors |
| 指導教授: |
王水進
Wang, Shui-Jinn |
| 學位類別: |
博士 Doctor |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
| 論文出版年: | 2014 |
| 畢業學年度: | 102 |
| 語文別: | 英文 |
| 論文頁數: | 118 |
| 中文關鍵詞: | 氧化銦鎵鋅 、高介電係數 、薄膜電晶體 、金屬基極電晶體 |
| 外文關鍵詞: | InGaZnO, high-k, thin-film transistor, Schottky diode, metal-base transistor |
| 相關次數: | 點閱:103 下載:0 |
| 分享至: |
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近年來針對以氧化物半導體作為通道材料的薄膜電晶體的研究已取得極大之進展,同時在商業化產品中也已出現以氧化銦鎵鋅薄膜電晶體作為主動式陣列之面板。預期在未來的面板產業乃至於次世代整合於透明面板之邏輯系統的開發上,氧化物半導體將扮演舉足輕重的角色。為了能夠改善氧化物半導體薄膜電晶體的電性效能包含操作電壓降低、載子遷移率提升、元件漏電流抑制、閘極操作能力提升以及拓展氧化物半導體元件的應用範疇,本論文中先以高介電係數閘極介電層與氧化銦鎵鋅通道層濺鍍膜進行具較佳閘極控制能力、低電壓電晶體之製作,接著針對此一元件架構,進行包含源/汲極電極區域之能帶工程與氧化銦鎵鋅通道層低熱預算雷射退火製程,以期分別降低漏電流與提升載子遷移率與元件驅動力。另一方面,本論文亦將針對可方便於垂直式整合之電晶體設計,進行以氧化銦鎵鋅製作之金屬基極電晶體之開發,藉由調變製程氣體中氧氣含量與於半導體與金屬間置入一介面層以降低Fermi level pinning效應與增強其蕭基特性,並將深入探討以兩個氧化銦鎵鋅蕭基二極體對接堆疊製作之氧化銦鎵鋅金屬基極薄膜電晶體元件操行為以及進行電流放大性能提升之研究。
氧化銦鎵鋅薄膜為一非晶態且具有較非晶矽為高之載子移動率、可允許室溫製程之半導體材料,非常適合應於大面積及軟性電子之應用。於以濺鍍製程製作氧化銦鎵鋅薄膜電晶體方面,本論文分別針對薄膜電晶體之三大核心系統,包含(1)閘極/閘極介電層/通道層;(2)源/汲極電極接觸與(3)半導體通道層分別進行獨立之研究以提供不同面向之改善方針。首先,本論文針對閘極/閘極介電層/通道層此一電晶體核心部分進行改善,利用高介電係數閘極介電層氧化矽鉿來提升氧化銦鎵鋅薄膜電晶體的整體特性。改善後的氧化矽鉿/氧化銦鎵鋅薄膜電晶體具有臨限電壓0.005 V、次臨界擺幅0.11 V/dec、載子移動率12.7 cm2/Vs以及電流開關比3×105的特性 (@VD = 1.0 V)。此外,我們探討了這種高介電係數材料分別經過300-500oC的熱處理之後對元件特性的影響。由實驗結果顯示,使用高介電係數氧化矽鉿閘極介電層製作之氧化銦鎵鋅薄膜電晶體在經過400oC之熱退火時,所得特性最佳。
其次,於導入高介電係數閘極介電層氧化矽鉿之元件架構下,本論文進一步針對氧化鎵銦鋅薄膜電晶體源/汲極電極區域之能帶工程進行研究,我們以低濃度氧化錫經由共濺鍍製程摻雜入氧化鎵銦鋅後製作出具較低載子濃度之淺摻雜區域以提升在源/汲極接觸面上之蕭基能障與空乏區寬度。此一具備氧化錫銦鎵鋅電子阻障層的氧化鎵銦鋅薄膜電晶體相較於未包含源/汲極電極區域電子阻障層之電晶體具有較低臨限電壓0.55 V、較高電流開關比1.9×106 (@VD = 1.0 V)、優良移動率13.39 cm2/Vs以及極低的次臨界擺幅0.073 V/dec,並且能夠在調變臨限電壓與關閉電壓的同時有效減少載子移動率與驅動電流的降低。
另一方面,有別於電極區域之能帶工程,於使用濺鍍製程製備之氧化銦鎵鋅薄膜電晶體之通道特性調變研究方面,藉由低熱預算之248奈米準分子雷射進行氧化銦鎵鋅通道之沉積後退火處理來提升載子移動率,可局部針對通道材料進行短時間高溫退火避免影響前段製程的閘極介電材料之特性。經調整雷射脈衝之能量密度於0~400 mJ/cm2範圍之製程,最佳之元件特性為退火雷射能量密度達300 mJ/cm2時,氧化銦鎵鋅薄膜內部溫度可超過1000oC,此條件下氧化鎵銦鋅薄膜電晶體具有高電流開關比3.5×105、優良移動率17.8 cm2/Vs、非常低的次臨界擺幅0.075 V/dec。
本論文中第四部分亦進行以大氣電漿噴塗法製作氧化銦鎵鋅通道搭配氧化鋁(25 nm)與二氧化鉿(25 nm)閘極介電層製備之氧化銦鎵鋅薄膜電晶體,相較於濺鍍製程其具有低設備成本與適合大面積與大量生產之優勢,並經由氨氣電漿處理以降低閘極漏電流及提升閘極電容進而優化元件特性。實驗中,以大氣電漿噴塗法製作之氧化銦鎵鋅薄膜電晶體經過30瓦的氨氣電漿60秒之處理後可獲得極佳的元件特性:其場效載子移動率達6.1 cm2/Vs遠高於一般使用水溶液法與噴塗方式製作之氧化銦鎵鋅薄膜電晶體,同時其具有優異之次臨界擺幅0.19 V/dec與極佳之電流開關比達108 (@VD = 6.0 V)。
於最後一部分,有別於傳統平面式薄膜電晶體之元件架構,本論文進行以氧化銦鎵鋅半導體材料為主之垂直式金屬基極電晶體之開發與製作,垂直方向之元件結構具有利於與有機發光二極體陣列整合之優勢。藉由增加射極與汲極氧化銦鎵鋅半導體材料濺鍍製程氣體中氧氣之含量以降低金屬/半導體蕭基接面之氧空缺改善因半導體內部所含大量氧空缺造成之Fermi level pinning負面效應且同時降低接面處氧化銦鎵鋅半導體內部之載子濃度,以擴大接面空乏區寬度及減少穿隧漏電流。此外,搭配介面氧化層材料之導入以減緩金屬離子之交互擴散避免造成不利於蕭基接面產生之金屬化介面。最後並針對上接觸式與下接觸式不同方向性之氧化銦鎵鋅蕭基二極體選用不同之金屬(鈦與金)製作出具單一方向性的氧化銦鎵鋅蕭基二極體並以垂直整合的方式製作出金屬基極電晶體,此一金屬基極電晶體為目前文獻中極少數應用無機材料製作之金屬基極電晶體並展現極佳之電特性,其共射極電流增益達到2500及共基極電流增益極接近理想值(~0.9996),亦遠大於目前文獻中主流之有機材料與鈣鈦礦金屬基極電晶體。
綜合以上的結果,結合高介電係數與氧化銦鎵鋅的高性能平面式與垂直式元件將有將有機會被利用在未來包含系統面板與有機發光二極體面板之應用上並擴大非矽基材料之終端產品應用範疇。
Researches on Oxide-semiconductor-based thin-film transistors (TFTs) have advanced remarkably in recent years. Commercial display products using indium gallium zinc oxide (InGaZnO) active arrays have also been successfully demonstrated. It is highly expected that the oxide semiconductor could have a high potential for use in next-generation display and in system-on-panel application. To improve the electrical performance of InGaZnO TFTs, various technologies or schemes have been reported to lower driving-voltage, enhance carrier mobility, reduce leakage current, and improve gate control ability. In the present dissertation, to further polish the performance of InGaZnO TFTs, the use of sputtering deposited high- HfSiO layer as the gate dielectric to enhance the gate control ability of InGaZnO TFTs is demonstrated. Sequentially, band engineering at source/drain region of the TFT to reduce the leakage current and a post treatment for the channel material using a low thermal budget 248-nm excimer laser annealing to improve the mobility and the current driving ability of the device are proposed and investigated. In another aspect, high performance vertical InGaZnO metal-base transistors (MBTs) were fabricated successfully by vertically integrating two InGaZnO Schottky diodes. Oxygen doping of InGaZnO semiconductor and interlayer insertion between metal and InGaZnO semiconductor were employed to eliminate Fermi level pinning and to enhance Schottky behavior. The operation of the InGaZnO MBTs and the improvement of the current gain would be discussed in this dissertation as well.
Amorphous InGaZnO can be fabricated at room temperature with excellent performance, the higher mobility of the material as compared to the amorphous Si has promised the applications in large-scale display and flexible electronics. In this dissertation, the InGaZnO TFTs were fabricated by sputtering technique firstly. Different techniques were used to improve the device performance aim at three different parts of the device including: (1) the gate/gate dielectric/channel stacks, (2) the source/drain contact regions, and (3) the channel layer. In the first part, aimming at the gate/gate dielectric/ channel stacks, high- HfSiO gate dielectric were used to fabricate InGaZnO TFTs with a low driving voltage, The influence of post-deposition annealing (PDA) temperature in the range of 300-500oC for the HfSiO gate dielectric on device performance was studied.. In our experiments, the 400oC PDA HfSiO/a-InGaZnO TFT exhibits a low threshold voltage of 0.005 V, a small subthreshold swing (SS) of 0.11 V/dec, a high saturation mobility of 12.7 cm2/Vs, and an acceptable current ratio of 3×105 at VD = 1.0 V.
Next, using the high-κ HfSiO as gate dielectric, InGaZnO TFTs with a co-sputtered low doping tin indium gallium zinc oxide (SnInGaZnO) electron barrier layer (EBL) were fabricated to enhance the Schottky barrier height and to enlarge the depletion width at the source/drain contact regions. By stacking a 250-nm-thick SnInGaZnO EBL at the source/drain region, it shows that the turn-off voltage of TFTs increases from -0.5 to about 0 V, the on/off current ratio increases from 1.9×105 to 1.9×106 at VD = 1.0 V, and the subthreshold swing decreases from 0.13 to 0.073 V/dec while preserving a high mobility and current driving ability as compared to the device without the insertion of source/drain SnInGaZnO electron barrier layers.
In the third part of this dissertation, to adjust the characteristic of sputtering-fabricated InGaZnO channel of TFT without degrading the front-end dielectric film, 248-nm KrF excimer laser annealing (ELA) with energy density between 0 and 400 mJ/cm2 were applied and the influence on the electrical behavior of InGaZnO TFTs is investigated. The experimental results show that the internal temperature in InGaZnO can be as high as 1000oC, the most improved device performance is obtained with high on/off current ratio of 3.5×105 at VD = 1.0 V, excellent mobility of 17.8 cm2/Vs and low subthreshold swing of 0.073 V/dec by applying a 300 mJ/cm2 laser pulse.
In the fourth part of this dissertation, InGaZnO TFTs were fabricated by atmospheric pressure plasma jet (APPJ) technique with the advantages including low apparatus cost and better suitability for large-scale and mass production than the sputtering process. HfO2 (25 nm) and Al2O3 (25 nm) were used as the gate dielectric stacks. NH3 plasma treatment is applied to optimize the device performance by reducing the gate dielectric leakage and increasing the oxide capacitance. The best performance of the APPJ InGaZnO TFT is obtained with a 30 W-60 s NH3 plasma treatment with field-effect mobility of 6.1 cm2/Vs which is much higher than the reported InGaZnO TFTs fabricated with solution-process or spray techniques, it also shown excellent subthreshold swing of 0.19 V/dec, and on/off current ratio of 108 at VD = 1.0 V.
In the last part of this dissertation, in addition to the conventional coplanar TFTs, the vertical InGaZnO MBTs were fabricated by integrating the top-contacted Au/HfSiO/InGaZnO and bottom-contacted Ti/InGaZnO Schottky diodes as emitter and collector of the MBT, respectively. The InGaZnO Schottky diodes (Ti/InGaZnO and Au/HfSiO/InGaZnO) were fabricated through oxygen doping and HfSiO interlayer insertion to eliminate Fermi level pinning and to enhance Schottky behavior attribute to the lowered oxygen vacancies, the widened depletion width at the junction, and the avoiding of inter-diffusion of the metal cations. Different metals (Ti and Au) were chosen for the fabrication of the uni-directional Schottky diodes depending on their reactivity to the oxygen atoms. Till now, few in-organic materials were reported to use for the fabrication of MBT, the high common-emitter current gain (β = 2500) and high common-base current gain (α = 0.9996) obtained from the InGaZnO MBT are much higher than the reported current gains in organic and perovoskite MBTs.
From the results mentioned above, the integration of the high-κ gate dielectric with the InGaZnO semiconductor in both co-planar (TFTs) and vertical device (MBTs) structures have shown excellent electrical performance, which could be very promising for application in system-on-panel (SoP) and organic light-emitting (OLED) display in the future.
Chapter 1
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Chapter 2
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Chapter 3
[3.1] Kenji Nomura, Hiromichi Ohta, Kazushige Ueda, Toshio Kamiya, Masahiro Hirano, and Hideo Hosono, “Thin-Film Transistor Fabricated in Single-Crystalline Transparent Oxide Semiconductor,” Science, vol. 300, no. 5623, pp. 1269-1272, May 2003.
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Chapter 4
[4.1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-Temperature Fabrication of Transparent Flexible Thin-Film Transistors Using Amorphous Oxide Semiconductors,” Nature, vol. 432, pp. 488-492, Nov. 2004.
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Chapter 5
[5.1] K. Nomura, H.Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature Fabrication of Transparent Flexible Thin-film Transistors Using Amorphous Oxide Semiconductors,” Nature, vol. 432, pp. 488-492, Nov. 2004.
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Chapter 6
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校內:2019-08-22公開