掃描測試技術已經廣泛地使用於測試數位電路。就系統單晶片(SOC)設計而言，測試時間及功率消耗已經成為使用掃描測試技術時所遇到的兩項關鍵性的問題。在本論文中，我們將針對掃描設計電路提出可以降低掃描測試時間及功率消耗的技術。
首先，我們發展一項測試多組待測電路的新式掃描測試技術。此技術可大幅度降低掃描測試時間且允許只使用單一條輸入資料線提供測試向量給多條掃描線電路。此技術之主要觀念是利用多組待測電路的測試向量間具有“共享”的特性。在執行自動向量產生(ATPG)的過程中，藉由適當地連接多組待測電路之輸入線，使得所產生的測試向量能夠在實際進行測試時以廣播(broadcast)的方式傳送測試向量給所有的掃描線。因此可以有效地解決測試時間過久的問題。我們的技術也同時針對週邊掃描架構(Boundary scan, IEEE 1149.1)及多條掃描線設計之間的整合問題，提供了一個低成本且高效率的解決方法。由實驗結果可知，此技術只需要157組測試向量便可完全偵測到10個ISCAS’85組合電路中所有可偵測到的錯誤；此外，只需要280組測試向量便可完全偵測到ISCAS’89順序電路中10個較大的待測電路之所有可偵測到的錯誤。
對掃描測試電路而言，除了測試時間過久的問題之外，測試功率消耗亦是另一項關鍵性的問題。在本論文的第二部份，我們發展了Multiple Clock Disabling (MCD)及Pseudo-Full Scan (PFS) 這兩種新穎的掃描測試架構以達到同時降低掃描測試時間及功率消耗的目的。我們的方法為靈活地修改及整合數種已存在的測試向量產生技術以產生一組特殊的測試向量，並使得此組測試向量適用於MCD及PFS掃描架構之中。此兩種掃描測試架構是藉由1. 將測試向量壓縮成一較短的序列及2. 於測試過程中只對部份之暫存器執行掃描動作以降低掃描測試時間及功率消耗。在ISCAS’85及ISCAS’89電路的實驗結果中顯示，MCD及PFS這兩種技術都可以大幅度降低掃描測試時間及功率消耗。此外，就PFS架構而言，我們只需要轉換電路中少部份的暫存器成為掃描暫存器便能達到全掃描設計之錯誤涵蓋率。

Scan-based techniques have been widely used to test digital circuits. For a system-on-a-chip (SOC) design, long test application time and excess power dissipation are becoming two critical problems for scan-based testing. In this dissertation, several novel techniques are proposed to reduce test application time and power dissipation for scan-based circuits.

First, we develop a novel test methodology that not only substantially reduce the test application time for multiple circuits but also allows a single input data line to support multiple scan chains. The main idea of this methodology is to explore the "sharing" property of test patterns among all circuits under test (CUTs). By appropriately connecting the inputs of all CUTs during ATPG process such that the generated test patterns can be broadcast to all scan chains when the actual testing operation is executed, the problem of long test application time can be solved effectively. Our method also provides a low cost and high performance method to integrate the Boundary scan and multiple scan test architectures. Experimental results show that 157 test patterns are enough to detect all detectable faults in the ten ISCAS'85 combinational circuits, while 280 test patterns are enough for the ten largest ISCAS'89 scan-based sequential circuits.

In addition to the problem of long test application time, test power consumption is becoming quite critical for testing scan-based circuits. In the second part of this dissertation, we develop two novel scan architectures called the multiple clock disabling (MCD) and the pseudo-full scan (PFS) to reduce test application time and test power dissipation simultaneously. Our methods are made possible by cleverly modifying and integrating a number of existing test generation techniques to generate a special set of test patterns that is suitable for scan architectures based on the MCD and PFS techniques. The two methods reduce test application time and power consumption by (1)compressing the test vector sequence into a much shorter one, and (2) scanning only a subset of the flip-flops. Experimental results for the ISCAS'85 and ISCAS'89 benchmark circuits show that both the MCD and PFS architectures can achieve significant reduction on both test application time and power dissipation compared to the conventional scan method. For the PFS architecture, experimental results also show that many flip-flops can be left unscanned while full-scan fault coverage is still obtained.

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