電流汲取式數位類比轉換器(Current-steering DAC)雖具備良好的高速操作適應性，如何兼具良好的線性度以降低系統成本仍是一大課題。本論文將針對有限輸出阻抗所造成的非線性因子進行更進一步分析，利用數位輸入碼與輸出阻抗的關係提出一與數位類比轉換器匹配之自適應輸出阻抗補償技術，在提高操作速度的同時能進一步補償有限阻抗效應以提升線性度；此技術不需要額外的數位運算及控制電路，且使數位類比轉換器可採用輸出阻抗較小的非疊接式(Non-cascoded)電流單元來實現，讓系統成本得以大幅降低。本論文一共實現兩顆晶片，除上述技術外，每顆晶片亦採用新提出的不同技術來改善線性度。
第一顆支援無線通訊之數位類比轉換器晶片以40奈米製程實作，並採用實驗室先前發展的二元權重隨機選取技術與同心平行四邊形繞線法來針對電流源之間隨機及梯度不匹配的非線性問題；再者，為解決數位類比轉換器輸入碼切換時在輸出端所造成的碼相依切換突波，本論文亦採用實驗室先前發展的切換突波補償器來大幅改善切換突波帶來的碼相依失真問題；數位電路採用時序交錯(Time-interleaving)之架構來搭配分散式佈局，同時增加數位運算的可靠性；最後，此晶片支援超奈奎斯特(Over-Nyquist)運作，使數位類比轉換器可以操作在第二奈奎斯特頻寬(2nd Nyquist band)且輸出頻率能達到取樣率。此晶片面積為1.45平方毫米、主動面積為0.12平方毫米；量測結果顯示，此數位類比轉換器可直接合成0 ~ 5.2GHz之輸出訊號，並於第一及第二奈奎斯特頻寬(0 ~ 2.6GHz及2.6 ~ 5.2GHz)分別達到無雜散動態範圍(SFDR)高於63dBc及42dBc，其可直接合成之信號涵蓋藍芽、Wifi 6、4G及5G-sub 6GHz之通訊應用，且量測結果之綜合性能指標(FoM)為近年最佳40奈米高速數位類比轉換器(取樣率高於2GHz)文獻的1.8倍。
第二顆支援高達Ku頻帶之數位類比轉換器晶片則延續第一顆晶片，採用寄生效應更低的28奈米製程以達到更高的規格並提出新式數位類比轉換器架構。電流單元陣列採用分散式佈局以降低電容效應，並提出一新式分割同心平行四邊形繞線法割繞法，以維持梯度不匹配的改善效果；此晶片提出一個新式超奈奎斯特數位類比轉換器實現方法，利用斬波器(Chopper)搭配驅動電路來達成超奈奎斯特運作，並且利用展頻設計以最小化支援超奈奎斯特運作所造成的頻寬下降，使DAC在提高輸出頻率下可維持良好的線性度。此晶片面積為0.82平方毫米、主動面積為0.067平方毫米，根據全晶片佈局後模擬結果顯示，此數位類比轉換器可以達成0 ~ 20GHz之訊號直接合成，並於第一及第二奈奎斯特頻寬(0 ~ 10GHz及10 ~ 20GHz)分別達到無雜散動態範圍高於60dBc及57dBc，和近年最佳兩篇高速高解析數位類比轉換器(位元數 ≥ 10，取樣率 ≥ 6GHz)文獻的綜合性能指標擬合包絡線相比，此晶片的綜合性能指標在輸出頻率為10GHz及20GHz下分別高出4倍及2.14倍。

Although current-steering DACs have potential for high-speed operation, maintaining well linearity with a high data rate is still a major issue. In this thesis, the non-linearity factors from the finite output impedance are further analyzed. Based on the relationship between the input code and output impedance, a technique of adaptive output impedance compensation (AOIC) matching with the DAC is proposed. The AOIC technique suppresses the finite output impedance effect during a high-speed operation without additional digital logics or control circuits. Moreover, the AOIC makes non-cascoded current sources feasible, and thus the system cost can be significantly reduced. Two chips are realized in this thesis, and other than the technique mentioned above, different proposed techniques are also adopted into each chip for improving the DAC’s linearity.
The 1st chip implements a DAC supporting wireless communication in the 40nm process. The random-rotated-based selection (RRBS) technique and concentric parallelogram routing (CPR) from our lab are adopted for random and gradient mismatch issues. A switching glitch compensation (SGC) from our lab is also adopted for suppressing the output distortion which is caused by the inter-symbol-dependent switching glitch. The time-interleaving structure is adopted in the digital circuit for a higher circuit reliability. Finally, this chip supports the over-Nyquist operation which enables DAC’s 2nd Nyquist band and achieves the highest output frequency up to the sampling rate. The chip size is 1.45 mm2 and the active area is 0.12 mm2. The measurement results show that this DAC can directly synthesize the signal from 0 to 5.2GHz and achieve the spurious free dynamic range (SFDR) > 63dBc and > 42dBc in the 1st and 2nd Nyquist bands (0~2.6GHz and 2.6~5.2GHz) respectively. The synthesized signal frequency can cover Bluetooth, Wifi 6, 4G and 5G-sub 6GHz applications, and this work has a 1.8x higher figure-of-merit (FoM) compared to the state-of-the-art 40nm CMOS DACs with a sampling rate ≥ 2GHz.
The 2nd chip realizes a DAC supporting communication applications up to Ku-band. Based on the 1st chip, this DAC adopts the 28nm process for lower parasitic effect and a new structure is proposed for a higher bandwidth. The distributed layout for the current cell array is applied for capacitance reduction, with a proposed “Split-CPR” layout method to maintain the gradient mismatch suppression. Moreover, a new implementation of the over-Nyquist operation is proposed using a chopper combining with the bandwidth extended driving circuit, which minimizes the bandwidth degradation due to supporting the over-Nyquist operation. This DAC consumes 0.82 mm2 chip area and 0.067 mm2 active area. Corresponding to the whole chip post-layout-simulation results, this DAC can directly synthesize the signal from 0 to 20GHz and achieve the SFDR > 57dBc in the entire 20GHz bandwidth of the 1st and 2nd Nyquist bands. Compared to the envelope fitting with the two best FoM of previous state-of-the-art high-speed high-resolution DACs (bit number ≥ 10 and sampling rate ≥ 6GHz), this DAC achieves a 4x-better FoM with fout equal to 10GHz and a 2.14x-better FoM with fout equal to 20GHz.

[1] S. Su and M. S. -W. Chen, "A Time-Approximation Filter for Direct RF Transmitter," IEEE J. Solid-State Circuits, vol. 56, no. 7, pp. 2018-2028, July 2021
[2] V. Ravinuthula, W. Bright, M. Weaver, K. Maclean, S. Kaylor, S. Balasubramanian, J. Coulon, R. Keller, B. Nguyen, and E. Dwobeng, “A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz”, in IEEE Symp. VLSI Circuits (VLSIC), June 2016, pp. 1-2.
[3] L. Duncan, B. Dupaix, J. J. McCue, B. Mathieu, M. LaRue, V. J. Patel, M. Teshome, M.-J. Choe, and W. Khalil, “A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR,” IEEE J. Solid-State Circuits, vol. 52, no. 12, pp. 3262–3275, Dec. 2017.
[4] C. Erdmann, E. Cullen, D. Brouard, R. Pelliconi, B. Verbruggen, J. Mcgrath, D. Collins, M. De La Torre, P. Gay, P. Lynch, P. Lim, A. Collins, and B. Farley, “A 330mW 14b 6.8GS/s Dual-Mode RF DAC in 16nm FinFET Achieving -70.8dBc ACPR in a 20MHz Channel at 5.2GHz,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 280–281.
[5] D. Gruber et al., "A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET," IEEE J. Solid-State Circuits, vol. 56, no. 12, pp. 3655-3667, Dec. 2021
[6] P. Caragiulo, O. E. Mattia, A. Arbabian and B. Murmann, "A 2x Time-Interleaved 28-GS/s 8-Bit 0.03-mm2 Switched-Capacitor DAC in 16-nm FinFET CMOS," IEEE J. Solid-State Circuits, vol. 56, no. 8, pp. 2335-2346, Aug. 2021
[7] W.-T. Lin, H.-Y. Huang, and T.-H. Kuo, “A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique,” IEEE J.Solid-State Circuits, vol. 49, no. 3, pp. 708–717, Mar. 2014.
[8] S. Luschas and H. S. Lee, “Output impedance requirements for DACs,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2003, pp. I-861–I-864.
[9] C.-H. Lin, F. M. L. van der Goes, J. R. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu, and K. Bult, “A 12 bit 2.9 GS/s DAC With IM3< -60 dBc Beyond 1 GHz in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3285–3293, Dec. 2009.
[10] P. Palmers and M. S. J. Steyaert, “A 10-Bit 1.6-GS/s 27-mW current-steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 11, pp. 2870–2879, Nov. 2010.
[11] Wei-Hsin Tseng, Chi-Wei Fan, and Jieh-Tsorng Wu, “A 12-Bit 1.25-GSps DAC in 90 nm CMOS with over 70 dB SFDR up to 500 MHz,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2845-2856, Dec. 2011.
[12] Ali Nazemi, et. Al., “A 36Gb/s PAM4 Transmitter Using an 8b 18GS/s DAC in 28nm CMOS” in IEEE ISSCC Dig. Tech. Papers, Feb. 2015, pp. 58–59.
[13] Tao Chen, and Georges G. E. Gielen, “A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2386-2394, Nov. 2007.
[14] Wei-Te Lin, and Tai-Haur Kuo, “A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection,” IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 444-453, Feb. 2012.
[15] Geert A. M. Van der Plas, Jan Vandenbussche, Willy Sansen, Michel S. J. Steyaert, and Georges G. E. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999.
[16] H. -Y. Huang and T. -H. Kuo, "A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation," in IEEE Symp. VLSI Circuits (VLSIC), June 2019, pp. C136-C137.
[17] H. -Y. Huang, X. -Y. Chen and T. -H. Kuo, "A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < −77dBc IM3," in IEEE Symp. VLSI Circuits (VLSIC), June 2020, pp. 1-2.
[18] L. Lai, X. Li, Y. Fu, Y. Liu and H. Yang, "Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 1, pp. 68-81, Jan. 2019.
[19] Hsu, Fu-Sheng (2010), “A 14-bit 200MHz DAC with Minimum Current Switching and Dynamic Element Matching for Oversampling and Nyquist Dual-Mode,” National Cheng Kung University, Tainan.
[20] Alex R. Bugeja, Bang-Sup Song, Patrick L. Rakers, and Steven F. Gillig, “A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1719-1732, Dec. 1999.
[21] Chen, Xin-Yu (2019), “A 14-bit 10GS/s DAC with Switching Glitch Compensation,” National Cheng Kung University, Tainan.
[22] S. Spiridon, H. Yan and H. Eberhart, "A linearity improvement technique for overcoming signal-dependent induced switching time mismatch in DAC-Based transmitters," ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, pp. 347-347c
[23] Huang, Hung-Yi (2020), “Linearization Techniques for High-Speed High-Resolution Current-Steering Digital-to-Analog Conversion,” National Cheng Kung University, Tainan.