| 研究生: |
王聖宏 Wang, Sheng-Hong |
|---|---|
| 論文名稱: |
適用於公開金鑰密碼學系統之以4為基底的低延遲可擴充性蒙哥馬利乘法器 Low-Latency Scalable Radix-4 Montgomery Multiplier for Public Key Cryptosystem |
| 指導教授: |
謝明得
Shieh, Ming-Der |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2012 |
| 畢業學年度: | 100 |
| 語文別: | 中文 |
| 論文頁數: | 56 |
| 中文關鍵詞: | 蒙哥馬利乘法器 、RSA 公開金鑰密碼處理器 、支援雙領域計算蒙哥馬利乘法器 |
| 外文關鍵詞: | Montgomery multiplier, RSA cryptography processor, Dual-field Montgomery multiplier |
| 相關次數: | 點閱:67 下載:1 |
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模乘法運算 (Modular Multiply)近年來被大量應用在公開金鑰密碼學系統,像是RSA(Rivest-Sharmir-Adleman) 密碼學系統或是ECC(Elliptic Curve Cryptography)密碼學系統。而模乘法運算在公開金鑰密碼學系統中一直是相當重要且嚴苛的運算。在目前被提出的模乘法運算演算法之中,蒙哥馬利模乘法演算法是一個非常有效率的方法。在論文中,我們提出了一個以字元為基準,具可擴充性,並搭載低延遲技術之以4 為基底的布斯編碼(Booth encoding)蒙哥馬利乘法器架構。
在傳統以4 為基底的蒙哥馬利模乘法運算中,由於迴圈的暫時運算結果都必須向右位移而造成資料相依性關係問題,使得相鄰處理單元之間的時間延遲必須等兩個時間週期。而在我們論文中所提出來的架構中,提出了低延遲時間的方法,無論我們選用哪一種字元大小,相鄰處理單元之間的時間延遲都會縮減為一個時間週期,資料相依性關係問題得到舒解,而此方法不需要增加運算元個數。
此新技術的實作成果顯示,和其他以4 為基底的蒙哥馬利模乘法器相比較,我們所提出的設計可以節省完成一次1024 位元蒙哥馬利乘法26.5%的運算時間。
Modular multiplication is widely applied to public key cryptosystems like Rivest-Sharmir-Adleman (RSA) and elliptic curve cryptography (ECC).Modular multiplication is always an important and crucial operation in public key cryptosystems. Among existing modular multiplication algorithms, Montgomery’s modular multiplication algorithm is known as a very efficient method for carrying out modular multiplication. This work presents a word-based Booth encoded radix-4 Montgomery modular multiplication algorithm for low-latency scalable architecture.
The data dependency resulting from the inherent right shifting of the intermediate results in the conventional radix-4 Montgomery modular multiplication algorithm is alleviated; thus the latency between neighboring process elements (PEs) is exactly one cycle regardless of the chosen word size. Moreover, the number of the equivalent operands in the accumulation is not increased with operand reduction scheme.
Implementation results show that compared to other Booth encoded radix-4 Montgomery modular multipliers, the proposed design can achieve at least 26.5% time reduction for accomplishing one 1024-bit Montgomery modular multiplication.
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