| 研究生: |
陳冠仲 Chen, Kuan-Chung |
|---|---|
| 論文名稱: |
SIMT/MIMD雙模多核心處理器系統架構之研究 A Study of SIMT/MIMD Dual-Mode Multi-Core Processor System Architecture |
| 指導教授: |
陳中和
Chen, Chung-Ho |
| 學位類別: |
博士 Doctor |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2018 |
| 畢業學年度: | 106 |
| 語文別: | 英文 |
| 論文頁數: | 98 |
| 中文關鍵詞: | 執行緒分歧 、資料平行度 、多執行緒架構 、開放運算語言 、多指令多資料處理器 、單指令多執行緒處理器 、基於時空之單指令多執行緒運算 |
| 外文關鍵詞: | Control divergence, Data level parallelism, Multithreading, Open Computing Language OpenCL, MIMD processors, SIMT processors, Spatiotemporal SIMT |
| 相關次數: | 點閱:132 下載:24 |
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單指令多執行緒機器在高效能運算領域中是一種主流的計算機架構。其主要原因為單指令多執行緒運算模型可有效運用資料平行度達成輸出取向的計算方法。本篇論文探討此單指令多執行緒的運算模型應用於傳統同質性多核心中央處理器的可行性與好處;而在此之前,大多數的多核心中央處理器僅支援多指令多資料的運算模型。為了使多核心中央處理器支援單指令多執行緒運算模型,我們提出了三個計算機架構上所需解決的議題,包含有:多執行緒運算模型實現、核心執行緒內文儲存方式以及執行緒分支所造成效能損失之問題。
我們整合了單指令多執行緒運算模型於ARM多核心處理器架構中。為此目的,我們提出一套可應用在傳統多核心中央處理器系統的細質多執行緒運算模型。為了滿足細質多執行緒運算於每個執行週期切換執行執行緒的需求,在執行單指令多執行緒運算期間,每個處理器核心的L1快取記憶體將被用來儲存核心執行緒內文。而為了分歧密集的運算核心,我們提出一套名為“內圈條件運算式優先”的機制來達成執行緒分歧提前聚合以有效提升運算效能。與傳統多指令多執行緒模型相比,在單指令輸入循序處理器(single issue in-order processor)中採用單指令多執行緒模型執行OpenCL核心,平均可減少36%執行指令數,並且可達到平均1.52倍與高達5倍的速度提升。而在執行向量優化的OpenCL核心時,單指令多執行緒模型可額外得到單指令多資料擴展指令集(SIMD extension)的好處,因而比多指令多執行緒運算加速1.71倍。而單指令多執行緒模型也可應用於超純量循序(superscalar in-order)處理器架構,並且在執行效能上勝過超純量亂序(superscalar out-of-order)處理器40個百分比。實驗結果顯示本論文所提出的雙模運算架構在提升多核心處理器系統對於資料平行度的利用效率上扮演著至關重要的角色。
SIMT machine emerges as a primary computing device in high performance computing since the SIMT execution paradigm can exploit data-level parallelism effectively. This dissertation explores the SIMT execution potential on homogeneous multi-core processors, which generally run in MIMD mode when utilizing the multi-core resources. We address three architecture issues in enabling SIMT execution model on multi-core processor, including multithreading execution model, kernel thread context placement, and thread divergence.
For the SIMT execution model, we propose a fine-grained multithreading mechanism on an ARM-based multi-core system. Each of the processor cores stores the kernel thread contexts in its L1 data cache for per-cycle thread-switching requirement. For divergence-intensive kernels, an Inner Conditional Statement First (ICS-First) mechanism helps early re-convergence to occur and significantly improves the performance. The experiment results show that effectiveness in data-parallel processing reduces on average 36% dynamic instructions, and boosts the SIMT executions to achieve on average 1.52x and up to 5x speedups over the MIMD counterpart for OpenCL benchmarks for single issue in-order processor cores. By using the explicit vectorization optimization on the kernels, the SIMT model gains further benefits from the SIMD extension and achieves 1.71x speedup over the MIMD approach.The SIMT model using in-order superscalar processor cores outperforms the MIMD model that uses superscalar out-of-order processor cores by 40 percent. This study shows that, to exploit data-level parallelism, enabling the SIMT model on homogeneous multi-core processors is important.
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